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Jung-Dal Choi

Jung-Dal Choi

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
37
Citations
5561
World Ranking
5144
National Ranking
178

Overview

Jung-Dal Choi is a researcher affiliated with SK Hynix in South Korea, contributing to fields intersecting computer science, engineering, and physics and astronomy. Their work encompasses subfields such as computer networks and communications, electrical and electronic engineering, and atomic and molecular physics and optics.

Their research primarily focuses on advanced data storage technologies, semiconductor materials and devices, and the magnetic properties of thin films. These thematic concentrations reflect a multidisciplinary approach to the study and development of modern electronic and memory systems.

Among the published works credited to Jung-Dal Choi is the 2022 paper titled A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 Density, presented at the 2022 IEEE International Solid-State Circuits Conference (ISSCC). This publication addresses improvements in memory density and latency within the context of next-generation NAND flash memory design.

Frequent coauthors collaborating with Jung-Dal Choi include:

  • Wanik Cho
  • Jongseok Jung
  • Jongwoo Kim
  • Junghoon Ham
  • Sang-Kyu Lee

Jung-Dal Choi's presence in scholarly venues is noted notably in the IEEE International Solid-State Circuits Conference (ISSCC), where their contributions are situated within a broader professional dialogue on semiconductor and circuit advances.

The scope of Jung-Dal Choi's research activity is evident through an integrated focus on device-level innovations and fundamental material properties, contributing to evolving technology in the semiconductor industry and data storage fields. This profile illustrates an active engagement across multiple scientific and engineering disciplines, pertinent to advancements in electronic component design and performance.

Best Publications

  • Effects of floating-gate interference on NAND flash memory cell operation

    Jae-Duk Lee;Sung-Hoi Hur;Jung-Dal Choi

  • Three-dimensional semiconductor memory device

    Sunil Shim;Jang-Gn Yun;Jeonghyuk Choi;Kwang Soo Seol

  • Methods of fabricating floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers

    Chang-Hyun Lee;Jung-Dal Choi;Byoung-Woo Ye

  • High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond

    H.J. Oh;J.Y. Kim;J.H. Kim;S.G. Park

  • A 3.3 V 1 Gb multi-level NAND flash memory with non-uniform threshold voltage distribution

    Taehee Cho;Young-Taek Lee;Euncheol Kim;Jinwook Lee

  • A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes

    Taehee Cho;Yeong-Taek Lee;Eun-Cheol Kim;Jin-Wook Lee

  • Non-volatile semiconductor memory devices

    Chang-Hyun Lee;Jung-Dal Choi;Byoung-Woo Ye

  • A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM)

    Seong-Geon Park;Min Kyu Yang;Hyunsu Ju;Dong-Jun Seong

  • Non-volatile memory devices and methods of operating the same

    Chang-Hyun Lee;Jung-Dal Choi

  • The non-volatile memory device with NAND cell structure includes plural memory cell serials, BLs & selective transistors at 1st & 2nd memory cell serials are separately serial with BL contact & 2 ends of memory cell.

    Choi Jung-Dal;Kim Dong-Jun;Shin Wang-Chul;Kim Jong-Han

  • Future Outlook of NAND Flash Technology for 40nm Node and Beyond

    Kinam Kim;Jungdal Choi

  • Highly Manufacturable 32Gb Multi -- Level NAND Flash Memory with 0.0098 μm 2 Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology

    Youngwoo Park;Jungdal Choi;Changseok Kang;Changhyun Lee

  • Non-volatile memory device and method for fabricating the same

    Chang-Hyun Lee;Jung-Dal Choi;Byung-Kwan You;Sung-Hoi Hur

  • A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs

    Yoocheol Shin;Jungdal Choi;Changseok Kang;Changhyun Lee

  • 3D approaches for non-volatile memory

    Jungdal Choi;Kwang Soo Seol

  • 8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology

    Jong-Ho Park;Sung-Hoi Hur;Joon-Hee Leex;Jin-Taek Park

  • Method of forming non-volatile memory having floating trap type device

    Chang-Hyun Lee;Jung-Dal Choi;Sung-Hoi Hur

  • Semiconductor device having fin-type field effect transistor and method of manufacturing the same

    Sung Gi Hur;TaeYong Kwon;Sangsu Kim;Jungdal Choi

  • Nonvolatile memory device with NAND cell strings

    Ki-tae Park;Jung-Dal Choi

  • Non-Volatile Memory Devices

    Hyun Suk Kim;Sun-II Shim;Chang-seok Kang;Won-Cheol Jeong

Frequent Co-Authors

Kinam Kim
Kinam Kim Samsung (South Korea)
Ki-Tae Park
Ki-Tae Park Samsung (South Korea)
Sanghun Jeon
Sanghun Jeon Korea Advanced Institute of Science and Technology
Jang-Sik Lee
Jang-Sik Lee Pohang University of Science and Technology
Jae-Hoon Jang
Jae-Hoon Jang Samsung (South Korea)
Byung-Gook Park
Byung-Gook Park Seoul National University

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