World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
42
Citations
6874
World Ranking
4132
National Ranking
1479

Overview

What is he best known for?

The fields of study he is best known for:

  • Semiconductor
  • Electrical engineering
  • Optoelectronics

Johann Alsmeier focuses on Optoelectronics, Electrical engineering, Semiconductor, Substrate and Dielectric. His Optoelectronics study integrates concerns from other disciplines, such as Electronic engineering and Layer, Gate oxide, Substrate, Etching. His research in Electronic engineering intersects with topics in Electrical conductor and Insulator.

Air gap and Wafer is closely connected to Trench in his research, which is encompassed under the umbrella topic of Electrical engineering. His work in Substrate addresses issues such as Perpendicular, which are connected to fields such as Blocking and Etching. His work in Dielectric tackles topics such as Silicide which are related to areas like Gate dielectric.

His most cited work include:

  • Ultrahigh density vertical nand memory device and method of making thereof (495 citations)
  • Method of making a vertical nand device using sequential etching of multilayer stacks (206 citations)
  • Ultrahigh density vertical nand memory device & method of making thereof (187 citations)

What are the main themes of his work throughout his whole career to date?

His primary scientific interests are in Optoelectronics, Semiconductor, Substrate, Dielectric and Electrical engineering. The study incorporates disciplines such as Layer, Trench, Semiconductor device and Electronic engineering in addition to Optoelectronics. His work on Intrinsic semiconductor as part of general Semiconductor study is frequently linked to Pedestal, bridging the gap between disciplines.

His study in Substrate is interdisciplinary in nature, drawing from both Electrical conductor, Non-volatile memory, Etching and Source lines. His study on High-κ dielectric is often connected to Fabrication, Front and Trapping as part of broader study in Dielectric. His studies deal with areas such as Silicide, Perpendicular and Thin-film transistor as well as Electrical engineering.

He most often published in these fields:

  • Optoelectronics (82.64%)
  • Semiconductor (35.54%)
  • Substrate (33.88%)

What were the highlights of his more recent work (between 2016-2021)?

  • Optoelectronics (82.64%)
  • Stack-based memory allocation (23.97%)
  • Substrate (33.88%)

In recent papers he was focusing on the following fields of study:

Johann Alsmeier spends much of his time researching Optoelectronics, Stack-based memory allocation, Substrate, Electrically conductive and Layer. A large part of his Optoelectronics studies is devoted to Semiconductor. Substrate is the subject of his research, which falls under Composite material.

His Layer research includes themes of Electrical connection and Dielectric. His Dielectric study integrates concerns from other disciplines, such as Trench and Dielectric isolation. His studies in Line integrate themes in fields like Structural engineering, Conductive materials and Dielectric layer.

Between 2016 and 2021, his most popular works were:

  • Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof (32 citations)
  • Three-dimensional memory device containing hydrogen diffusion barrier structures for CMOS under array architecture and method of making the same (16 citations)
  • Three-dimensional memory device containing separately formed drain select transistors and method of making thereof (12 citations)

In his most recent research, the most cited papers focused on:

  • Cell region
  • Semiconductor
  • Transistor

His scientific interests lie mostly in Optoelectronics, Line, Electrically conductive, Layer and Multi tier. His study in the field of Dielectric is also linked to topics like Diffusion. His Line research incorporates elements of Transistor and Dielectric layer.

The concepts of his Layer study are interwoven with issues in Field-effect transistor, Doping and High voltage. Many of his Multi tier research pursuits overlap with Conductive materials and Structural engineering.

Best Publications

  • Ultrahigh density vertical nand memory device and method of making thereof

    Johann Alsmeier

  • Method of making an ultrahigh density vertical NAND memory device with shielding wings

    Johann Alsmeier;George Samachisa

  • Method of making a vertical nand device using sequential etching of multilayer stacks

    Raghuveer S. Makala;Yao-Sheng Lee;Jayavel Pachamuthu;Johann Alsmeier

  • Multilevel memory stack structure and methods of manufacturing the same

    Jayavel Pachamuthu;Johann Alsmeier;Henry Chien

  • Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device

    Peter Rabkin;Jayavel Pachamuthu;Johann Alsmeier

  • Vertical nand and method of making thereof using sequential stack etching and landing pad

    Chi-Ming Wang;Johann Alsmeier;Henry Chien;Xiying Costa

  • Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device

    Raghuveer S. Makala;Johann Alsmeier;Yao-Sheng Lee

  • Ultrahigh density vertical NAND memory device

    Johann Alsmeier

  • Selective word line erase in 3D non-volatile memory

    Yingda Dong;Alex Mak;Seungpil Lee;Johann Alsmeier

  • Three-dimensional non-volatile memory device

    Jayavel Pachamuthu;Johann Alsmeier;Raghuveer S. Makala;Yao-Sheng Lee

  • High aspect ratio memory hole channel contact formation

    Jayavel Pachamuthu;Johann Alsmeier;Raghuveer S. Makala;Yao-Sheng Lee

  • Method of making ultrahigh density vertical NAND memory device

    Johann Alsmeier

  • Three dimensional NAND device with silicide containing floating gates

    Henry Chien;Johann Alsmeier;George Samachisa;Henry Chin

  • Method of making a three-dimensional memory array with etch stop

    Yao-Sheng Lee;Johann Alsmeier

  • Three dimensional nand device with semiconductor, metal or silicide floating gates and method of making thereof

    Raghuveer S. Makala;Johann Alsmeier

  • 3d semicircular vertical nand string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same

    James K. Kai;Yanli Zhang;Henry Chien;Johann Alsmeier

  • Cobalt-containing conductive layers for control gate electrodes in a memory structure

    Raghuveer S. Makala;Rahul Sharangpani;Sateesh Koka;Genta Mizuno

  • Metal replacement process for low resistance source contacts in 3d nand

    Matthias Baenninger;Johann Alsmeier;Akira Matsudaira;Jayavel Pachamuthu

  • Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors

    Zhenyu Lu;Daxin Mao;Koji Miyata;Junichi Ariyoshi

  • Three-dimensional nand device containing support pedestal structures for a buried source line and method of making the same

    James Kai;Johann Alsmeier;Jin Liu;Yanli Zhang

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