World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
38
Citations
5762
World Ranking
4927
National Ranking
1715

Research.com Recognitions

  • 2008 - IEEE Fellow For contributions to deep sub-micron foundry CMOS technology

Overview

What is he best known for?

The fields of study he is best known for:

  • Semiconductor
  • Transistor
  • Integrated circuit

Carlos H. Diaz mainly investigates Optoelectronics, MOSFET, Electrical engineering, CMOS and Gate oxide. His work carried out in the field of Optoelectronics brings together such families of science as Semiconductor device, Nanotechnology and Leakage. In general Electrical engineering study, his work on Transistor, AND gate and NMOS logic often relates to the realm of Conductivity, thereby connecting several areas of interest.

His Transistor research incorporates themes from Doping, Semiconductor and Power semiconductor device. His CMOS study which covers Shallow trench isolation that intersects with Dopant, Cmos logic circuits, Stress effects, Circuit design and Threshold voltage. In his study, Field-effect transistor is strongly linked to Gate dielectric, which falls under the umbrella field of Gate oxide.

His most cited work include:

  • Pi-Gate SOI MOSFET (264 citations)
  • Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane (77 citations)
  • A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics (76 citations)

What are the main themes of his work throughout his whole career to date?

His main research concerns Optoelectronics, Layer, Semiconductor device, Electrical engineering and Semiconductor. Carlos H. Diaz has researched Optoelectronics in several fields, including Substrate, Gate dielectric, Gate oxide and MOSFET. His MOSFET research is multidisciplinary, relying on both Silicon on insulator, Electron mobility and Leakage.

His Layer research is multidisciplinary, incorporating elements of Nanowire and Dielectric. In his research on the topic of Semiconductor device, Shallow trench isolation is strongly related with Electronic engineering. Carlos H. Diaz interconnects Wafer, Non-volatile memory and Second source in the investigation of issues within Semiconductor.

He most often published in these fields:

  • Optoelectronics (76.99%)
  • Layer (28.87%)
  • Semiconductor device (25.10%)

What were the highlights of his more recent work (between 2015-2021)?

  • Optoelectronics (76.99%)
  • Layer (28.87%)
  • Semiconductor device (25.10%)

In recent papers he was focusing on the following fields of study:

His scientific interests lie mostly in Optoelectronics, Layer, Semiconductor device, Semiconductor and Dielectric layer. His studies in Optoelectronics integrate themes in fields like Transistor and Substrate. His Layer research incorporates elements of Non-volatile memory, Silicon, Ferroelectricity and Integrated circuit.

The various areas that he examines in his Semiconductor device study include Structure and Metal gate. Line and Trench is closely connected to Hard mask in his research, which is encompassed under the umbrella topic of Semiconductor. His Dielectric layer study combines topics from a wide range of disciplines, such as Substrate, Negative impedance converter, Nano- and MOSFET.

Between 2015 and 2021, his most popular works were:

  • Semiconductor devices and methods of manufacture thereof (18 citations)
  • Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs (18 citations)
  • InAs FinFETs With $ extrm {H}_{\mathrm {fin}}=20$ nm Fabricated Using a Top–Down Etch Process (18 citations)

In his most recent research, the most cited papers focused on:

  • Semiconductor
  • Transistor
  • Integrated circuit

His primary scientific interests are in Optoelectronics, Layer, Semiconductor device, Semiconductor and Transistor. He combines subjects such as Trench and Substrate, Gate oxide with his study of Optoelectronics. His Gate oxide study necessitates a more in-depth grasp of Electrical engineering.

His work in Semiconductor device addresses issues such as Structure, which are connected to fields such as Electronic engineering. His Semiconductor research includes elements of Non-volatile memory, Doping and Epitaxy. The Sram cell research Carlos H. Diaz does as part of his general Transistor study is frequently linked to other disciplines of science, such as Transition metal, therefore creating a link between diverse domains of science.

Best Publications

  • Pi-Gate SOI MOSFET

    Jong-Tae Park;J.-P. Colinge;C.H. Diaz

  • An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

    C.H. Diaz;Hun-Jan Tao;Yao-Ching Ku;A. Yen

  • Dynamic gate coupling of NMOS for efficient output ESD protection

    C. Duvvury;C. Diaz

  • Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

    Chien-Hao Chen;T.L. Lee;T.H. Hou;C.L. Chen

  • Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design

    B. Kleveland;C.H. Diaz;D. Vook;L. Madden

  • Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane

    Jean Pierre Colinge;Carlos H. Diaz

  • Monolithic CMOS distributed amplifier and oscillator

    B. Kleveland;C.H. Diaz;D. Vock;L. Madden

  • Self-aligned wrapped-around structure

    Jean-Pierre Colinge;Kuo-Cheng Ching;Ta-Pen Guo;Carlos H. Diaz

  • Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect

    Howard Chih-Hao Wang;Su-Yu Lu;Mu-Chi Chiang;Carlos H. Diaz

  • Multi-Gate Device and Method of Fabrication Thereof

    Kuo-Cheng Ching;Ching-Wei Tsai;Carlos H. Diaz;Chih-Hao Wang

  • A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

    Ke-Wei Su;Yi-Ming Sheu;Chung-Kai Lin;Sheng-Jier Yang

  • MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)

    Chang-Hoon Choi;Jung-Suk Goo;Tae-Young Oh;Zhiping Yu

  • Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices

    C.H. Diaz;Sung-Mo Kang;C. Duvvury

  • CMOS technology for MS/RF SoC

    C.H. Diaz;D.D. Tang;J.Y.-C. Sun

  • Silicon and silicon germanium nanowire formation

    Kuo-Cheng Ching;Carlos H. Diaz;Jean-Pierre Colinge

  • Leakage scaling in deep submicron CMOS for SoC

    Yo-Sheng Lin;Chung-Cheng Wu;Chih-Sheng Chang;Rong-Ping Yang

  • Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs

    Yi-Ming Sheu;Sheng-Jier Yang;Chih-Chiang Wang;Chih-Sheng Chang

  • Device and method of manufacture for protection against plasma charging damage in advanced MOS technologies

    Carlos H. Diaz

  • Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping

    Mark J. H. van Dal;Georgios Vellianitis;Blandine Duriez;Gerben Doornbos

  • Demonstration of scaled Ge p-channel FinFETs integrated on Si

    M.J.H. van Dal;G. Vellianitis;G. Doornbos;B. Duriez

Frequent Co-Authors

Jean-Pierre Colinge
Jean-Pierre Colinge University of California, Davis
Yee-Chia Yeo
Yee-Chia Yeo National University of Singapore
Fu-Liang Yang
Fu-Liang Yang Academia Sinica
J.Y.-C. Sun
J.Y.-C. Sun National Taiwan University
Chenming Hu
Chenming Hu University of California, Berkeley
Mong-Song Liang
Mong-Song Liang Taiwan Semiconductor Manufacturing Company (United States)
Sung-Mo Kang
Sung-Mo Kang University of California, Santa Cruz
Jhon-Jhy Liaw
Jhon-Jhy Liaw Taiwan Semiconductor Manufacturing Company (Taiwan)
Thomas H. Lee
Thomas H. Lee Stanford University
Lars-Erik Wernersson
Lars-Erik Wernersson Lund University

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