Jhon-Jhy Liaw

Overview

Best Publications

• Method of forming static random access memory (SRAM) and layout of SRAM

  Liaw Jhon-Jhy

  523
  Citations

• Memory cell structure

  Jhon-Jhy Liaw

  209
  Citations

• A 16nm FinFET CMOS technology for mobile SoC and computing applications

  Shien-Yang Wu;C. Y. Lin;M. C. Chiang;J. J. Liaw

  195
  Citations

• SRAM cell design with high resistor CMOS gate structure for soft error rate improvement

  Jhon-Jhy Liaw

  156
  Citations

• Methods for operating a FinFET SRAM array

  Jhon-Jhy Liaw

  154
  Citations

• A 7nm CMOS platform technology featuring 4 th generation FinFET transistors with a 0.027um 2 high density 6-T SRAM cell for mobile SoC applications

  Shien-Yang Wu;C.Y. Lin;M.C. Chiang;J.J. Liaw

  150
  Citations

• 13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-V MIN applications

  Jonathan Chang;Yen-Huei Chen;Wei-Min Chan;Sahil Preet Singh

  135
  Citations

• Semiconductor structure and method for forming the semiconductor structure

  Liaw Jhon-Jhy

  126
  Citations

• FinFET Memory Device

  Jhon-Jhy Liaw

  125
  Citations

• Method for metal gate structure for MOS devices

  Jhon-Jhy Liaw

  108
  Citations

• Leakage scaling in deep submicron CMOS for SoC

  Yo-Sheng Lin;Chung-Cheng Wu;Chih-Sheng Chang;Rong-Ping Yang

  93
  Citations

• Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process

  Jhon-Jhy Liaw;Dun-Nian Yaung;Jin-Yuan Lee

  92
  Citations

• Semiconductor device with improved contact structure and method of forming same

  Jhon-Jhy Liaw

  91
  Citations

• Method of forming a static random access memory with a buried local interconnect

  Jhon-Jhy Liaw

  90
  Citations

• An enhanced 16nm CMOS technology featuring 2 nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

  Shien-Yang Wu;C.Y. Lin;M.C. Chiang;J.J. Liaw

  88
  Citations

• Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure including a straight walled sidewall spacer while filling recess

  Jhon-Jhy Liaw

  86
  Citations

• Fuse window guard ring structure for nitride capped self aligned contact processes

  Jhon-Jhy Liaw

  75
  Citations

• A 25-nm gate-length FinFET transistor module for 32nm node

  Chang-Yun Chang;Tsung-Lin Lee;Clement Wann;Li-Shyue Lai

  75
  Citations

• Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer

  Jhon-Jhy Liaw;Jin-Yuan Lee;Kuei-Ying Lee;Chu-Yun Fu

  71
  Citations

• Methods and apparatus for FinFET SRAM cells

  Jhon-Jhy Liaw

  71
  Citations