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Fariborz Assaderaghi

Fariborz Assaderaghi

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
41
Citations
6631
World Ranking
4305
National Ranking
1529

Overview

Fariborz Assaderaghi is affiliated with SiTime in the United States. Their professional focus appears to be rooted in scientific research, though specific details about their research topics, published papers, and contributions to scientific literature are limited based on the available data.

No recent papers attributed to Fariborz Assaderaghi are listed, and there are no noted frequent co-authors or frequent publication venues associated with their work. Similarly, no book publications or awards have been documented in the provided information.

Information regarding main fields of study, subfields, or main topics of work is also not available. This suggests either a specialized area outside of commonly tracked academic categories or limited public documentation of their research output.

Given the affiliation with SiTime-a company known for technology development in timing solutions and semiconductor devices-it may be inferred that Fariborz Assaderaghi's work could relate to areas involving microelectronics, timing technology, or related engineering fields, although this is not explicitly stated in the data.

Without citations, paper titles, or detailed subject matter, a more precise characterization of Fariborz Assaderaghi's scientific contributions cannot be provided. The absence of listed awards or other recognitions similarly restricts further contextualization of their academic or professional impact.

Best Publications

  • Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

    F. Assaderaghi;D. Sinitsky;S.A. Parke;J. Bokor

  • A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation

    F. Assaderaghi;D. Sinitsky;S. Parke;J. Bokor

  • Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation

    Chenming Hu;Hsing-Jen Wann

  • Mixed memory integration with NVRAM, dram and sram cell structures on same substrate

    Fariborz Assaderaghi;Louis Lu-Chen Hsu;Jack A. Mandelman

  • T-RAM array having a planar cell structure and method for fabricating the same

    Louis L. Hsu;Rajiv V. Joshi;Fariborz Assaderaghi

  • Two-device memory cell on SOI for merged logic and memory applications

    Fariborz Assaderaghi;Bijan Davari;Louis L. Hsu;Jack A. Mandelman

  • IMPROVED SOI FET DESIGN TO REDUCE TRANSISTOR BIPOLAR CURRENT

    Mario M A Pelella;Fariborz Assaderaghi;Lawrence Frederick Wagner

  • A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

    F. Assaderaghi;S. Parke;D. Sinitsky;J. Bokor

  • Method and system for improving the performance on SOI memory arrays in an SRAM architecture system

    Louis L. Hsu;Rajiv V. Joshi;Fariborz Assaderaghi;Mary J. Saccamango

  • Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET

    C. Wann;F. Assaderaghi;R. Dennard;Chenming Hu

  • Double SOI device with recess etch and epitaxy

    Fariborz Assaderaghi;Tze-Chiang Chen;K. Muller;Edward Nowak

  • High-field transport of inversion-layer electrons and holes including velocity overshoot

    F. Assaderaghi;D. Sinitsky;J. Bokor;P.K. Ko

  • Method of making large value capacitor for SOI

    Fariborz Assaderaghi;Louis L. Hsu;Jack A. Mandelman;William R. Tonti

  • Partially-depleted SOI technology for digital logic

    G.G. Shahidi;A. Ajmera;F. Assaderaghi;R.J. Bolam

  • A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With $ Frequency Stability and $ Integrated Jitter

    M. H. Perrott;J. C. Salvia;F. S. Lee;A. Partridge

  • The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta

    J. Chen;F. Assaderaghi;P.-K. Ko;C. Hu

  • Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation

    Fariborz Assaderaghi;Louis Lu-Chen Hsu;Jack Allan Mandelman

  • Methods and circuits for asymmetric distribution of channel equalization between devices

    Jared L. Zerbe;Fariborz Assaderaghi;Brian S. Leibowitz;Hae-Chang Lee

  • Integrated circuit with built-in heating circuitry to reverse operational degeneration

    Gary Bronner;Brent S. Haukness;Fariborz Assaderaghi;Mark D. Kellam

  • Simulation Of Floating Body Effect In SOI Circuits Using BSIM3SOI

    R. Tu;D. Sinitsky;F. Assaderaghi;C. Wann

  • A novel Silicon-On-Insulator (SOI) MOSFET for ultra low voltage operation

    F. Assaderaghi;S. Parke;P.K. Ko;Chenming Hu

Frequent Co-Authors

Chenming Hu
Chenming Hu University of California, Berkeley
Ghavam G. Shahidi
Ghavam G. Shahidi IBM (United States)
Jack A. Mandelman
Jack A. Mandelman Independent Scientist / Consultant, US
Louis L. Hsu
Louis L. Hsu IBM (United States)
Ping-Keung Ko
Ping-Keung Ko Hong Kong University of Science and Technology
Steven H. Voldman
Steven H. Voldman Independent Scientist / Consultant, US
Jeffrey Bokor
Jeffrey Bokor University of California, Berkeley
Dominic J. Schepis
Dominic J. Schepis Global Foundries
Jeffrey W. Sleight
Jeffrey W. Sleight IBM (United States)
Mansun Chan
Mansun Chan Hong Kong University of Science and Technology

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