World's Best Scientists 2026 revealed!

D-Index & Metrics

Engineering and Technology

D-Index
30
Citations
4594
World Ranking
9757
National Ranking
2783

Overview

Anthony K. Stamper is affiliated with GlobalFoundries in the United States. Their professional activities are based within the United States.

Currently, no records of recent published papers, co-authors, or frequent publication venues are available for Anthony K. Stamper. Similarly, there are no listed book publications or specific fields of study associated with their research profile.

This absence of detailed publication data and specific research topics limits the ability to outline the scientist's contributions across particular domains or areas of expertise in academic literature.

No awards or honors have been documented for Anthony K. Stamper in the accessible data.

Additional information regarding the scientist's research focus, including subfields of study or principal topics of work, is not available from the provided information.

Best Publications

  • Damascene copper wiring optical image sensor

    James W. Adkisson;Jeffrey P. Gambino;Mark D. Jaffe;Robert K. Leidy

  • Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits

    D. R. Cote;S. V. Nguyen;A. K. Stamper;D. S. Armbrust

  • Double-sided integrated circuit chips

    Kerry Bernstein;Timothy Joseph Dalton;Jeffrey Peter Gambino;Mark David Jaffe

  • Reduced Cu interface diffusion by CoWP surface coating

    C.-K. Hu;L. Gignac;R. Rosenberg;E. Liniger

  • Methods for forming a bonded semiconductor substrate including a cooling mechanism

    Jeffrey P. Gambino;Anthony K. Stamper

  • Planar mems structures, fabrication methods thereof and reducing variation of a silicon layer of planar mems structures

    Dang Dinh;Doan Thai;Dunbar Iii George A;He Zhong-Xiang

  • Low resistance and inductance backside through vias and methods of fabricating same

    Mete Erturk;Robert A. Groves;Jeffrey Bowman Johnson;Alvin Jose Joseph

  • Exposed pore sealing post patterning

    Edward C. Cooney;John A. Fitzsimmons;Jeffrey P. Gambino;Stephen E. Luce

  • Device and methodology for reducing effective diel

    Edelstein Daniel C;Colburn Matthew E;Cooney Edward C;Dalton Timothy J

  • Cmos imager of eliminating high reflectivity interfaces

    James W Adkisson;Jeffrey P Gambino;Mark D Jaffe;Robert K Leidy

  • Post-fuse blow corrosion prevention structure for copper fuses

    Timothy H. Daubenspeck;Daniel C. Edelstein;Robert M. Geffken;William T. Motsiff

  • METHOD OF MANUFACTURING ELECTRONIC STRUCTURE

    Adams Charlotte;Stamper Anthony

  • Passive components in the back end of integrated circuits

    Anil K. Chinthakindi;Douglas D. Coolbaugh;Ebenezer E. Eshun;Zhong-Xiang He

  • Through wafer vias and method of making same

    Hanyi Ding;Alvin Jose Joseph;Anthony Kendall Stamper

  • Through wafer via and method of making same

    Hanyi Ding;Alvin Jose Joseph;Anthony Kendall Stamper

  • Line edge roughness and spacing effect on low-k TDDB characteristics

    F. Chen;J.R. Lloyd;K. Chanda;R. Achanta

  • Recessed bond pad

    Anthony K. Stamper;Sally J. Yankee

  • Low-temperature chemical vapor deposition processes and dielectrics for microelectronic circuit manufacturing at IBM

    D. R. Cote;S. V. Nguyen;W. J. Cote;S. L. Pennington

  • Damascene etchback for low ε dielectric

    Anthony K. Stamper;Vincent J. McGahay

  • Characterization of yttria-stabilized zirconium oxide buffer layers for high-temperature superconductor thin films

    J‐W. Lee;T. E. Schlesinger;A. K. Stamper;M. Migliuolo

  • Metallic capacitor and its formation method

    M Jeffken Robert;Anthony K Stamper;アンソニー・ケイ・スタンパー;ロバート・エム・ジェフケン

  • Interconnect structures on substrate and its manufacture method

    Fitzsimmons John A;Stamper Anthony K;Dalton Timothy J;Cooney Iii Edward C

  • SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD AS WELL AS FORMING METHOD OF POLYSILICON FUSE AT THE SMALL PITCH IN SEMICONDUCTOR

    Anthony K Stamper

  • Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material

    Anil Kumar Chinthakindi;Douglas Duane Coolbaugh;Keith Edward Downes;Ebenezer E. Eshun

  • Dual wired integrated circuit chips

    Kerry Bernstein;Timothy Joseph Dalton;Jeffrey Peter Gambino;Mark David Jaffe

Frequent Co-Authors

Jeffrey P. Gambino
Jeffrey P. Gambino ON Semiconductor (United States)
Douglas D. Coolbaugh
Douglas D. Coolbaugh University at Albany, State University of New York
Christopher V. Jahnes
Christopher V. Jahnes IBM (United States)
Edmund J. Sprogis
Edmund J. Sprogis IBM (United States)
Alvin J. Joseph
Alvin J. Joseph GlobalFoundries (United States)
Terence B. Hook
Terence B. Hook IBM (United States)
Daniel C. Edelstein
Daniel C. Edelstein IBM (United States)
Matthew E. Colburn
Matthew E. Colburn Facebook (United States)
David L. Harame
David L. Harame IBM (United States)
Steven H. Voldman
Steven H. Voldman Independent Scientist / Consultant, US

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