Maud Vinet

Overview

Best Publications

• A CMOS silicon spin qubit.

  R. Maurand;X. Jehl;D. Kotekar-Patil;A. Corna

  638
  Citations

• The future transistors

  Unknown

  469
  Citations

• Advances, challenges and opportunities in 3D CMOS sequential integration

  P. Batude;M. Vinet;B. Previtali;C. Tabone

  325
  Citations

• Single-donor ionization energies in a nanoscale CMOS channel

  M. Pierre;R. Wacquez;X. Jehl;M. Sanquer

  315
  Citations

• Advances in 3D CMOS sequential integration

  P. Batude;M. Vinet;A. Pouydebasque;C. Le Royer

  304
  Citations

• 22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications

  R. Carter;J. Mazurier;L. Pirro;J-U. Sachse

  293
  Citations

• Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

  O. Faynot;F. Andrieu;O. Weber;C. Fenouillet-Beranger

  237
  Citations

• 3D monolithic integration: Technological challenges and electrical results

  M. Vinet;P. Batude;C. Tabone;B. Previtali

  235
  Citations

• Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors

  P. Coudrain;P. Batude;X. Gagnard;C. Leyris

  190
  Citations

• Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length

  P. Batude;M. Vinet;C. Xu;B. Previtali

  184
  Citations

• 3D monolithic integration

  P. Batude;M. Vinet;A. Pouydebasque;C. Le Royer

  181
  Citations

• Electrical Spin Driving by g-Matrix Modulation in Spin-Orbit Qubits.

  Alessandro Crippa;Romain Maurand;Léo Bourdet;Dharmraj Kotekar-Patil

  173
  Citations

• Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening

  Unknown

  173
  Citations

• Multiple gate devices: advantages and challenges

  T. Poiroux;M. Vinet;O. Faynot;J. Widiez

  170
  Citations

• CIRCUIT A TRANSISTOR INTEGRES DANS TROIS DIMENSIONS ET AYANT UNE TENSION DE SEUIL VT AJUSTABLE DYNAMIQUEMENT

  Batude Perrine;Clavelier Laurent;Jaud Marie Anne;Thomas Olivier

  159
  Citations

• Bonded planar double-metal-gate NMOS transistors down to 10 nm

  M. Vinet;T. Poiroux;J. Widiez;J. Lolivier

  153
  Citations

• 3DVLSI with CoolCube process: An alternative path to scaling

  P. Batude;C. Fenouillet-Beranger;L. Pasini;V. Lu

  150
  Citations

• Gate-based high fidelity spin readout in a CMOS device

  Matias Urdampilleta;David J Niegemann;Emmanuel Chanrion;Baptiste Jadot

  148
  Citations

• Performance and design considerations for gate-all-around stacked-NanoWires FETs

  S. Barraud;V. Lapras;B. Previtali;M. P. Samson

  146
  Citations

• GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

  L. Hutin;C. Le Royer;J.-F. Damlencourt;J.-M. Hartmann

  141
  Citations

• CELLULE DE MEMOIRE SRAM A TRANSISTOR INTEGRES SUR PLUSIEURS NIVEAUX ET DONT LA TENSION DE SEUIL VT EST AJUSTABLE DYNAMIQUEMENT

  Thomas Olivier;Batude Perrine;Pouydebbasque Arnaud;Vinet Maud

  136
  Citations

• Germanium on insulator and new 3D architectures opportunities for integration

  M. Vinet;C. Le Royer;P. Batude;J.-F. Damlencourt

  133
  Citations

• Simple and controlled single electron transistor based on doping modulation in silicon nanowires

  M. Hofheinz;X. Jehl;M. Sanquer;G. Molas

  131
  Citations

• Scaling silicon-based quantum computing using CMOS technology: State-of-the-art, Challenges and Perspectives

  M. F. Gonzalez-Zalba;S. de Franceschi;E. Charbon;T. Meunier

  7
  Citations