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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
37
Citations
6062
World Ranking
5107
National Ranking
97

Overview

Thomas Ernst is affiliated with Grenoble Alpes University in France and focuses primarily on engineering, with specific subfields including biomedical engineering, electrical and electronic engineering, bioengineering, cellular and molecular neuroscience, and mechanical engineering.

Their research covers a range of topics, with notable emphasis on analytical chemistry and sensors, nanowire synthesis and applications, neuroscience and neural engineering, advancements in semiconductor devices and circuit design, advanced memory and neural computing, modular robots and swarm intelligence, and gas sensing nanomaterials and sensors.

Thomas Ernst has published work in the following venues:

  • Sensors
  • IEEE Transactions on Electron Devices
  • Biosensors
  • Procedia CIRP
  • Advanced Engineering Materials

Recent papers attributed to Ernst include:

  • A Wearable Low-Power Sensing Platform for Environmental and Health Monitoring: The Convergence Project (2021, Sensors)
  • Label-Free C-Reactive Protein Si Nanowire FET Sensor Arrays With Super-Nernstian Back-Gate Operation (2022, IEEE Transactions on Electron Devices)
  • Lifecycle modeling for the eco design of the Internet of Things (2020, Procedia CIRP)
  • Neuron-Gated Silicon Nanowire Field Effect Transistors to Follow Single Spike Propagation within Neuronal Network (2020, Advanced Engineering Materials)
  • pH Quantification in Human Dermal Interstitial Fluid Using Ultra-Thin SOI Silicon Nanowire ISFETs and a High-Sensitivity Constant-Current Approach (2023, Biosensors)

Their collaborative network includes frequent coauthors such as Adrian M. Ionescu, Sylvain Barraud, Luca Capua, Yann Sprunger, and Hervé Elettro.

Best Publications

  • Ultimately thin double-gate SOI MOSFETs

    T. Ernst;S. Cristoloveanu;G. Ghibaudo;T. Ouisse

  • 3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS

    P. Batude;T. Ernst;J. Arcamone;G. Arndt

  • Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

    S. Barraud;M. Berthome;R. Coquand;M. Casse

  • A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

    A. Hubert;E. Nowak;K. Tachi;V. Maffini-Alvaro

  • Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

    O. Faynot;F. Andrieu;O. Weber;C. Fenouillet-Beranger

  • CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits

    Shashikanth Bobba;Ashutosh Chakraborty;Olivier Thomas;Perrine Batude

  • Improved split C-V method for effective mobility extraction in sub-0.1-/spl mu/m Si MOSFETs

    K. Romanjek;F. Andrieu;T. Ernst;G. Ghibaudo

  • Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

    M. Casse;L. Thevenod;B. Guillaumot;L. Tosti

  • Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture

    T. Ernst;T. Ernst;C. Tinella;C. Raynaud;S. Cristoloveanu

  • 15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

    C. Dupre;A. Hubert;S. Becu;M. Jublot

  • Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

    E. Bernard;T. Ernst;B. Guillaumot;N. Vulliet

  • Multiple gate devices: advantages and challenges

    T. Poiroux;M. Vinet;O. Faynot;J. Widiez

  • Engineering strained silicon on insulator wafers with the Smart CutTM technology

    B. Ghyselen;J.-M. Hartmann;T. Ernst;C. Aulnette

  • Performance and design considerations for gate-all-around stacked-NanoWires FETs

    S. Barraud;V. Lapras;B. Previtali;M. P. Samson

  • The last silicon transistor: Nanosheet devices could be the final evolutionary step for Moore's Law

    Unknown

  • Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO 2 gate stack

    V. Barral;T. Poiroux;F. Andrieu;C. Buj-Dufournet

  • Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features

    Thomas P. Ernst;Francois Andrieu;O. Weber;Jean-Michel Hartmann

  • Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

    T. Ernst;C. Dupre;C. Isheden;E. Bernard

  • Fully Depleted Silicon-on-Insulator nMOSFETs with Tensile Strained High Carbon Content Si1-yCy Channels

    Frédérique Ducroquet;Jean-Michel Hartmann;Claude Tabone;Dominique Lafond

  • Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid integration?

    T. Ernst;L. Duraffourg;C. Dupre;E. Bernard

  • A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs

    T. Ernst;R. Ritzenthaler;O. Faynot;S. Cristoloveanu

Frequent Co-Authors

O. Faynot
O. Faynot CEA LETI
Gerard Ghibaudo
Gerard Ghibaudo Grenoble Alpes University
Sorin Cristoloveanu
Sorin Cristoloveanu Grenoble Institute of Technology
Thomas Skotnicki
Thomas Skotnicki Warsaw University of Technology
B. De Salvo
B. De Salvo Meta for Business
Hiroshi Iwai
Hiroshi Iwai Tokyo Institute of Technology
Thierry Baron
Thierry Baron Grenoble Alpes University
S. Barraud
S. Barraud Atomic Energy and Alternative Energies Commission

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