World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
50
Citations
6511
World Ranking
2871
National Ranking
1082

Materials Science

D-Index
50
Citations
6663
World Ranking
10362
National Ranking
2462

Overview

What is he best known for?

The fields of study he is best known for:

  • Semiconductor
  • Optoelectronics
  • Electrical engineering

The scientist’s investigation covers issues in Optoelectronics, Electronic engineering, Dielectric, Gate dielectric and Layer. His studies in Optoelectronics integrate themes in fields like Electrical engineering, Gate oxide and Conductor. The Electronic engineering study combines topics in areas such as Ion implantation, Oxide, Capacitance and Silicon.

His Dielectric research is multidisciplinary, incorporating elements of Substrate, Trench, Semiconductor, Composite material and Deposition. His Gate dielectric research integrates issues from High-κ dielectric, Semiconductor device, Dielectric layer and Permittivity. In the subject of general Layer, his work in Polysilicon depletion effect and Photoresist is often linked to Communication channel, thereby combining diverse domains of study.

His most cited work include:

  • Substantially planar semiconductor topography using dielectrics and chemical mechanical polish (167 citations)
  • Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof (111 citations)
  • Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance (102 citations)

What are the main themes of his work throughout his whole career to date?

H. Jim Fulford spends much of his time researching Optoelectronics, Layer, Substrate, Electronic engineering and Gate oxide. His work carried out in the field of Optoelectronics brings together such families of science as Semiconductor device, Gate dielectric and Electrical engineering. His Layer study integrates concerns from other disciplines, such as Oxide and Masking.

His study focuses on the intersection of Substrate and fields such as Silicon with connections in the field of Wafer and Getter. As part of one scientific family, H. Jim Fulford deals mainly with the area of Electronic engineering, narrowing it down to issues related to the Dopant, and often Annealing and Barrier layer. His work in Dielectric addresses issues such as Semiconductor, which are connected to fields such as Chemical-mechanical planarization.

He most often published in these fields:

  • Optoelectronics (84.82%)
  • Layer (42.41%)
  • Substrate (37.74%)

What were the highlights of his more recent work (between 1998-2021)?

  • Optoelectronics (84.82%)
  • Layer (42.41%)
  • Gate oxide (36.96%)

In recent papers he was focusing on the following fields of study:

H. Jim Fulford mainly focuses on Optoelectronics, Layer, Gate oxide, Electrical engineering and Gate dielectric. His Optoelectronics study combines topics in areas such as Semiconductor device, Substrate, Electronic engineering, Substrate and Conductor. He has researched Substrate in several fields, including High-κ dielectric and Silicon.

As a part of the same scientific study, H. Jim Fulford usually deals with the Gate oxide, concentrating on Oxide and frequently concerns with Doping. His is involved in several facets of Electrical engineering study, as is seen by his studies on Electrical conductor and Integrated circuit. His Gate dielectric research incorporates elements of Drain-induced barrier lowering and Dielectric.

Between 1998 and 2021, his most popular works were:

  • Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit (78 citations)
  • Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication (68 citations)
  • Method of fabricating a transistor with a dielectric underlayer and device incorporating same (52 citations)

Best Publications

  • Substantially planar semiconductor topography using dielectrics and chemical mechanical polish

    Robert Dawson;Mark W. Michael;Basab Bandyopadhyay;H. Jim Fulford

  • Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof

    Mark I. Gardner;H. Jim Fulford;Charles E. May;Fred Hause

  • Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance

    Mark I. Gardner;Fred N. Hause;H. Jim Fulford

  • A method of forming high pressure silicon oxynitride (oxynitride) gate dielectrics for metal oxide semiconductor (mos) devices with p+ polycrystalline silicon (polysilicon) gate electrodes

    Dirk J. Wristers;H. Jim Fulford;Dim L. Kwong

  • Integrated circuit gate conductor which uses layered spacers to produce a graded junction

    H. Jim Fulford;Mark I. Gardner;Derick J. Wristers

  • Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant

    Mark I. Gardner;H. Jim Fulford;Dim-Lee Kwong

  • Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit

    Mark I. Gardner;H. Jim Fulford

  • Method of formation of an air gap within a semiconductor dielectric by solvent desorption

    H. Jim Fulford;Robert Dawson;Fred N. Hause;Basab Bandyopadhyay

  • Method and apparatus for in situ anneal during ion implant

    Robert Dawson;H. Jim Fulford;Mark I. Gardner;Frederick N. Hause

  • Dissolvable dielectric method and structure

    Fred N. Hause;Basab Bandyopadhyay;Robert Dawson;H. Jim Fulford

  • Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication

    Mark I. Gardner;H. Jim Fulford;Derick J. Wristers

  • CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein

    Mark I. Gardner;Fred N. Hause;H. Jim Fulford

  • Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

    Mark I. Gardner;Robert Dawson;H. Jim Fulford;Frederick N. Hause

  • Interlevel dielectric with air gaps to lessen capacitive coupling

    Basab Bandyopadhyay;H. Jim Fulford;Robert Dawson;Fred N. Hause

  • Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor

    Mark I. Gardner;H. Jim Fulford;Derrick J. Wristers

  • Method of channel doping using diffusion from implanted polysilicon

    H. Jim Fulford;Robert Dawson;Mark I. Gardner;Frederick N. Hause

  • Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate

    Mark I. Gardner;H. Jim Fulford

  • Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance

    Mark I. Gardner;Dim-Lee Kwong;H. Jim Fulford

  • Transistor with buried insulative layer beneath the channel region

    Bradley T. Moore;Robert Dawson;H. Jim Fulford;Mark I. Gardner

  • Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate

    Mark I. Gardner;H. Jim Fulford

  • Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

    Robert Dawson;Mark W. Michael;William S. Brennan;Basab Bandyopadhyay

Frequent Co-Authors

Mark I. Gardner
Mark I. Gardner Micron Technology
Derick J. Wristers
Derick J. Wristers Advanced Micro Devices (United States)

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