World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
32
Citations
4047
World Ranking
6348
National Ranking
2091

Research.com Recognitions

  • 2010 - IEEE Fellow For contributions to complementary metal oxide semiconductor device technology and on-chip electrostatic discharge protection

Overview

Amitava Chatterjee is affiliated with Texas Instruments in the United States. Their research primarily spans the fields of Engineering and Computer Science, with a focus on subfields including Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Biomedical Engineering, Artificial Intelligence, and Control and Systems Engineering.

The scientist's published work covers topics such as Robotics and Sensor-Based Localization, Non-Invasive Vital Sign Monitoring, Hand Gesture Recognition Systems, Indoor and Outdoor Localization Technologies, IoT-based Smart Home Systems, Advanced Fiber Optic Sensors, and Video Surveillance and Tracking Methods.

Frequent publication venues for Amitava Chatterjee include the IEEE Sensors Journal, IEEE Transactions on Instrumentation and Measurement, IEEE Sensors Letters, Journal of Building Performance Simulation, and Measurement Science and Technology.

  • PIR Sensor-Based AAL Tool for Human Movement Detection: Modified MCP-Based Dictionary Learning Approach, 2020, IEEE Transactions on Instrumentation and Measurement
  • Regularized K-SVD-Based Dictionary Learning Approaches for PIR Sensor-Based Detection of Human Movement Direction, 2020, IEEE Sensors Journal
  • Adaptive neural-bias-sliding mode control of rugged electrohydraulic system motion by recurrent Hermite neural network, 2020, Control Engineering Practice
  • Chaos-Based Random Sampling for Photometric Invariant Shoe Detection With Vision Sensor in Human-Robot Coexisting Environments, 2020, IEEE Sensors Journal
  • Rough Entropy-Based Fused Granular Features in 2-D Locality Preserving Projections for High-Dimensional Vision Sensor Data, 2023, IEEE Sensors Journal

Collaborative efforts have been made with frequent co-authors including Pritam Paral, Anjan Rakshit, Saibal Ghosh, Pubali De, and Kaushik Das Sharma.

Amitava Chatterjee was recognized as an IEEE Fellow in 2010 for contributions to complementary metal oxide semiconductor device technology and on-chip electrostatic discharge protection.

Best Publications

  • A low-voltage triggering SCR for on-chip ESD protection at output and input pads

    A. Chatterjee;T. Polgreen

  • Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow

    T.L. Polgreen;A. Chatterjee

  • A new three-terminal tunnel device

    S. Banerjee;W. Richardson;J. Coleman;A. Chatterjee

  • Low voltage triggering semiconductor controlled rectifiers

    Thomas L. Polgreen;Amitava Chatterjee;Ping Yang

  • Application of different isolation schemes for logic and embedded memory

    Kayvan Sadra;Alwin Tsao;Seetharaman Sridhar;Amitava Chatterjee

  • Method of making a silicon controlled rectifier device for electrostatic discharge protection

    Amitava Chatterjee

  • Shallow trench isolation for advanced ULSI CMOS technologies

    M. Nandakumar;A. Chatterjee;S. Sridhar;K. Joyner

  • Self-heating effects in basic semiconductor structures

    A. Amerasekera;M.-C. Chang;J.A. Seitchik;A. Chatterjee

  • CMOS metal replacement gate transistors using tantalum pentoxide gate insulator

    A. Chatterjee;R.A. Chapman;K. Joyner;M. Otobe

  • Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process

    A. Chatterjee;R.A. Chapman;G. Dixit;J. Kuehne

  • Semiconductor ESD protection circuit

    Charvaka Duvvury;Steven E. Marum;Amitava Chatterjee

  • Efficient ESD input protection scheme

    Amitava Chatterjee;Charvaka Duvvury

  • Hot electron reliability and ESD latent damage

    S. Aur;A. Chatterjee;T. Polgreen

  • Lateral SCR structure for ESD protection in trench isolated technologies

    E. Ajith Amerasekera;Bernhard H. Andresen;Amitava Chatterjee

  • Transistor design issues in integrating analog functions with high performance digital CMOS

    A. Chatterjee;K. Vasanth;D.T. Grider;M. Nandakumar

  • Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length and ultra-shallow junctions

    Amitava Chatterjee;Richard A. Chapman;Syed Suhail Murtaza

  • Comparative evaluation of gap-fill dielectrics in shallow trench isolation for sub-0.25 /spl mu/m technologies

    S. Nag;A. Chatterjee;K. Taylor;I. Ali

  • A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 /spl mu/m CMOS technologies and beyond

    A. Chatterjee;D. Rogers;J. McKee;I. Ali

  • BISTABLE PSEUDO SCR SWITCH FOR PROTECTING ESD OF SOI INTEGRATED CIRCUIT

    Chatterjee Amitava;Amerasekera E

  • Gate coupled SCR for ESD protection circuits

    Amitava Chatterjee;Charvaka Duvvury;Ping Yang;Ekanayake Ajith Amerasekera

Frequent Co-Authors

Theodore W. Houston
Theodore W. Houston Texas Instruments (United States)
Hisashi Shichijo
Hisashi Shichijo The University of Texas at Dallas
Sanjay K. Banerjee
Sanjay K. Banerjee The University of Texas at Austin
Roger K. Lake
Roger K. Lake University of California, Riverside
Gerhard Klimeck
Gerhard Klimeck Purdue University West Lafayette
Jerry M. Woodall
Jerry M. Woodall University of California, Davis
John D. Cressler
John D. Cressler Georgia Institute of Technology

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