His primary areas of study are Optoelectronics, Layer, Wafer, Electronic engineering and Optics. The study incorporates disciplines such as Transistor and Photoresist in addition to Optoelectronics. His research in Layer intersects with topics in Electrical conductor, Silicon and Dopant.
His work carried out in the field of Wafer brings together such families of science as Chip and Integrated circuit. His research in Electronic engineering tackles topics such as Conductor which are related to areas like Read-only memory, Diode and Groove. His study looks at the intersection of Optics and topics like Immersion lithography with Refractive index and Absorption.
Mark C. Hakey mainly investigates Optoelectronics, Layer, Electrical engineering, Electronic engineering and Nanotechnology. His studies deal with areas such as Trench, Substrate, Conductor and Semiconductor device as well as Optoelectronics. His study looks at the relationship between Substrate and fields such as Resist, as well as how they intersect with chemical problems.
His Layer research incorporates themes from Electrical conductor, Oxide and Dielectric. His work deals with themes such as Dram and Silicon on insulator, which intersect with Electrical engineering. His Silicon on insulator study combines topics in areas such as Wafer and Static random-access memory.
His primary areas of investigation include Optoelectronics, Layer, Electrical engineering, Dielectric and Electrical conductor. His Optoelectronics study frequently draws connections between related disciplines such as Substrate. His Layer study integrates concerns from other disciplines, such as Oxide, Electronic engineering and Optics.
The various areas that Mark C. Hakey examines in his Electrical engineering study include Heavy ion and Conductor. The Dielectric study combines topics in areas such as Resistor and Semiconductor device. His work investigates the relationship between Electrical conductor and topics such as Perpendicular that intersect with problems in Chip.
Mark C. Hakey mostly deals with Optoelectronics, Electrical engineering, Nanotechnology, Single event upset and Integrated circuit. Mark C. Hakey studies Doping, a branch of Optoelectronics. His work in the fields of Non-volatile memory and Resistor overlaps with other areas such as Series.
In the field of Nanotechnology, his study on Carbon nanotube and Phase-change memory overlaps with subjects such as Fluid dynamics. His Single event upset study combines topics from a wide range of disciplines, such as Radiation and Silicon on insulator. His biological study spans a wide range of topics, including Dimension, Structural engineering and Lithography.
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Accessible chip stack and process of manufacturing thereof
Furukawa Toshiharu Hakey Mark.
Novel structure for folded architecture pillar memory cell
Furukawa Toshiharu;Hakey Mark C;Holmes Steven J;Horak David.
MOVEMENT OF LENS FOR IMMERSION OPTICAL LITHOGRAPHY
Hakey Mark Charles;Horak David;Koburger Charles W;Mitchell Peter H.
Methods for forming uniform lithographic features
Toshiharu Furukawa;Mark Charles Hakey;Steven J. Holmes;David V. Horak.
SOI stacked DRAM logic
Ramachandra Divakauni;Mark C. Hakey;William H-L. Ma;Jack A. Mandclman.
Liquid-filled balloons for immersion lithography
Mark C. Hakey;David V. Horak;Charles W. Koburger;Peter H. Mitchell.
Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM
D.F. Heidel;P.W. Marshall;J.A. Pellish;K.P. Rodbell.
IEEE Transactions on Nuclear Science (2009)
System and apparatus for photolithography
Mark Charles Hakey;David Vaclay Horak;Charles William Koburger;Peter H. Mitchell.
Trench storage dynamic random access memory cell with vertical transfer device
Toshiharu Furukawa;Mark C. Hakey;David V. Horak;William H. Ma.
Low Energy Proton Single-Event-Upset Test Results on 65 nm SOI SRAM
D.F. Heidel;P.W. Marshall;K.A. LaBel;J.R. Schwank.
IEEE Transactions on Nuclear Science (2008)
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