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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
50
Citations
9314
World Ranking
2824
National Ranking
1067

Overview

Bharat L. Bhuva is affiliated with Vanderbilt University in the United States and has contributed extensively to the field of engineering, with a focus on electrical and electronic engineering. Their research spans over numerous subfields, including hardware and architecture, food science, molecular biology, and radiation.

Their scholarly output includes a significant number of publications in prominent venues. The most frequent publication outlet is the IEEE Transactions on Nuclear Science, with 32 papers. Other venues include the 2022 IEEE International Reliability Physics Symposium (IRPS), Food Bioscience, Microelectronics Reliability, and the Journal of Food Science.

Bhuva's research primarily addresses topics related to radiation effects in electronics, semiconductor materials and devices, and integrated circuits and semiconductor failure analysis. Additional areas of work involve VLSI and analog circuit testing, advancements in semiconductor devices and circuit design, low-power high-performance VLSI design, and physical unclonable functions (PUFs) and hardware security.

Notable recent papers include:

  • Single-Event Latchup in a 7-nm Bulk FinFET Technology, 2021, IEEE Transactions on Nuclear Science
  • Single-Event Upset Cross-Section Trends for D-FFs at the 5- and 7-nm Bulk FinFET Technology Nodes, 2022, IEEE Transactions on Nuclear Science
  • Single-Event Upsets in a 7-nm Bulk FinFET Technology With Analysis of Threshold Voltage Dependence, 2021, IEEE Transactions on Nuclear Science
  • Effect of Frequency on Total Ionizing Dose Response of Ring Oscillator Circuits at the 7-nm Bulk FinFET Node, 2022, IEEE Transactions on Nuclear Science
  • Study of Multicell Upsets in SRAM at a 5-nm Bulk FinFET Node, 2023, IEEE Transactions on Nuclear Science

Frequent collaborators in their research include Yoni Xiong, Dennis R. Ball, Nicholas J. Pieper, Rita Fung, and Shi-Jie Wen. These coauthors have worked alongside Bhuva in a variety of studies related to radiation effects and semiconductor device reliability.

Best Publications

  • Charge Collection and Charge Sharing in a 130 nm CMOS Technology

    O.A. Amusan;A.F. Witulski;L.W. Massengill;B.L. Bhuva

  • Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

    B. Narasimham;B.L. Bhuva;R.D. Schrimpf;L.W. Massengill

  • Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

    J.R. Ahlbin;L.W. Massengill;B.L. Bhuva;B. Narasimham

  • Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

    N. N. Mahatme;S. Jagannathan;T. D. Loveless;L. W. Massengill

  • RHBD techniques for mitigating effects of single-event hits using guard-gates

    A. Balasubramanian;B.L. Bhuva;J.D. Black;L.W. Massengill

  • Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

    T D Loveless;S Jagannathan;T Reece;J Chetia

  • On-Chip Characterization of Single-Event Transient Pulsewidths

    B. Narasimham;V. Ramachandran;B.L. Bhuva;R.D. Schrimpf

  • Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

    O.A. Amusan;L.W. Massengill;M.P. Baze;A.L. Sternberg

  • A Hardened-by-Design Technique for RF Digital Phase-Locked Loops

    T.D. Loveless;L.W. Massengill;B.L. Bhuva;W.T. Holman

  • Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process

    O.A. Amusan;L.W. Massengill;M.P. Baze;B.L. Bhuva

  • HBD layout isolation techniques for multiple node charge collection mitigation

    J.D. Black;A.L. Sternberg;M.L. Alles;A.F. Witulski

  • Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor

    L.W. Massengill;A.E. Baranski;D.O. Van Nort;J. Meng

  • A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS

    T.D. Loveless;L.W. Massengill;B.L. Bhuva;W.T. Holman

  • Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic

    O.A. Amusan;L.W. Massengill;B.L. Bhuva;S. DasGupta

  • Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology

    B.D. Olson;O.A. Amusan;S. Dasgupta;L.W. Massengill

  • Effect of Well and Substrate Potential Modulation on Single Event Pulse Shape in Deep Submicron CMOS

    S. DasGupta;A.F. Witulski;B.L. Bhuva;M.L. Alles

  • The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process

    J R Ahlbin;M J Gadlage;D R Ball;A W Witulski

  • Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

    N M Atkinson;A F Witulski;W T Holman;J R Ahlbin

  • Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes

    M J Gadlage;J R Ahlbin;B Narasimham;B L Bhuva

  • Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology

    K. Lilja;M. Bounasser;S.-J Wen;R. Wong

Frequent Co-Authors

Lloyd W. Massengill
Lloyd W. Massengill Vanderbilt University
Ronald D. Schrimpf
Ronald D. Schrimpf Vanderbilt University
Arthur F. Witulski
Arthur F. Witulski Vanderbilt University
Robert A. Reed
Robert A. Reed Vanderbilt University
Dale McMorrow
Dale McMorrow United States Naval Research Laboratory
Daniel M. Fleetwood
Daniel M. Fleetwood Vanderbilt University
Manoj Sachdev
Manoj Sachdev University of Waterloo
Paul E. Dodd
Paul E. Dodd Sandia National Laboratories
Eddy Simoen
Eddy Simoen Ghent University

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