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Shinichiro Kimura

Shinichiro Kimura

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
47
Citations
5951
World Ranking
3294
National Ranking
119

Overview

Shinichiro Kimura is affiliated with Hitachi in Japan and has contributed to the field of engineering, with a particular focus on electrical and electronic engineering. Their research portfolio encompasses multiple aspects of optical network technologies and polymer materials.

The scientist's recent publications highlight a blend of work in polymer chemistry and optical communication systems. Notable papers include:

  • A Temperature Responsive Polysaccharide Derivative in Aqueous Solution: Amylose Ethyl Carbamates (2020), published in ACS Applied Polymer Materials
  • Power saving control method with adaptive FEC decoder in optical access network (2024), published in IEICE Communications Express
  • A study on Low-Power Fully Differential Distributed Laser Driver Circuits with Gate-Line-Division Technique for Optical Access Networks (2025), published in IEICE Communications Express

The research topics covered by Shinichiro Kimura span several interconnected fields and subfields, such as:

  • Optical Network Technologies
  • Advanced Optical Network Technologies
  • Hydrogels: synthesis, properties, applications
  • Biodegradable polymer synthesis and properties
  • Surfactants and Colloidal Systems
  • Advanced Photonic Communication Systems
  • Semiconductor Lasers and Optical Devices

The main fields of study related to their work are:

  • Engineering
  • Electrical and Electronic Engineering
  • Molecular Medicine
  • Biomaterials
  • Organic Chemistry

Shinichiro Kimura's research has been frequently published in the following venues:

  • IEICE Communications Express
  • ACS Applied Polymer Materials

Throughout their career, they have collaborated with multiple coauthors, including:

  • Ryotaro Kochi
  • Shinichi Kitamura
  • Ken Terao
  • Kaito Kubo
  • Kariyawasam Indipalage Amila Sampath

Best Publications

  • Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control

    R. Tsuchiya;M. Horiuchi;S. Kimura;M. Yamaoka

  • Method of manufacturing a semiconductor device having silicon islands

    Dai Hisamoto;Toru Kaga;Shinichiro Kimura;Masahiro Moniwa

  • Promising storage capacitor structures with thin Ta/sub 2/O/sub 5/ film for low-power high-density DRAMs

    H. Shinriki;T. Kisu;S.-I. Kimura;Y. Nishioka

  • Limitations and challenges of multigigabit DRAM chip design

    K. Itoh;Y. Nakagome;S. Kimura;T. Watanabe

  • Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology

    M. Yamaoka;K. Osada;R. Tsuchiya;M. Horiuchi

  • Dynamic random access memory having trench capacitors and vertical transistors

    Shin'ichiro Kimura;Tokuo Kure;Toru Kaga;Digh Hisamoto

  • Method of manufacturing semiconductor memory cells and the same apparatus

    Matsuoka Hideyuki;Kimura Shinichiro;Yamanaka Toshiaki

  • Capacitive memory having a PN junction writing and tunneling through an insulator of a charge holding electrode

    Dai Hisamoto;Shoji Shukuri;Kazuhiko Sagara;Shinichiro Kimura

  • Low Temperature Oxidation of Silicon in a Microwave‐Discharged Oxygen Plasma

    Shin‐ichiro Kimura;Eiichi Murakami;Kiyoshi Miyake;Terunori Warabisako

  • Complementary MOS integrated circuits having vertical channel FETs

    Hideo Sunami;Makoto Ohkura;Shinichiro Kimura

  • Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics

    S. Tsujikawa;T. Mine;K. Watanabe;Y. Shimamoto

  • The impact of data-line interference noise on DRAM scaling

    Y. Nakagome;M. Aoki;S. Ikenaga;M. Horiguchi

  • A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THEREOF

    Kimura Shinichiro;Matsuoka Hideyuki;Nagai Ryo;Takaura Norikatsu

  • Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate

    N. Sugii;D. Hisamoto;K. Washio;N. Yokoyama

  • Electro-Luminescence from Ultra-Thin Silicon

    Shin‑ichi Saito;Digh Hisamoto;Haruka Shimizu;Hirotaka Hamamura

  • Semiconductor device and semiconductor memory device

    Dai Hisamoto;Toru Kaga;Shinichiro Kimura;Masahiro Moniwa

  • Dielectric Characteristics of Double Layer Structure of Extremely Thin Ta2 O 5 / SiO2 on Si

    Yasushiro Nishioka;Shin'ichiro Kimura;Hiroshi Shinriki;Kiichiro Mukai

  • Remote-charge-scattering limited mobility in field-effect transistors with SiO2 and Al2O3∕SiO2 gate stacks

    Shin-ichi Saito;Kazuyoshi Torii;Yasuhiro Shimamoto;Osamu Tonomura

  • A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

    H. Tanaka;M. Aoki;T. Sakata;S. Kimura

  • Method of making a semiconductor memory device with recessed array region

    Noboru Moriuchi;Yoshiki Yamaguchi;Toshihiko Tanaka;Norio Hasegawa

Frequent Co-Authors

Kiyoo Itoh
Kiyoo Itoh Hitachi (Japan)
Masanobu Miyao
Masanobu Miyao Kyushu University
Toshiro Hiramoto
Toshiro Hiramoto University of Tokyo
Takayuki Kawahara
Takayuki Kawahara Tokyo University of Science
Masashi Horiguchi
Masashi Horiguchi Hitachi (Japan)
Tsuyoshi Hasegawa
Tsuyoshi Hasegawa Waseda University

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