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Masashi Horiguchi

Masashi Horiguchi

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
31
Citations
3667
World Ranking
6617
National Ranking
287

Research.com Recognitions

  • 2010 - IEEE Fellow For contributions to circuit technologies for high-density low-power memories

Overview

Masashi Horiguchi is affiliated with Hitachi in Japan. Their recent research includes work published in the Journal of EMS Medicine, where they contributed a paper titled "Effects of the COVID-19 pandemic and the introduction of information and communication technology in emergency scenes on the emergency transport environment in Japan" in 2024.

Frequent co-authors collaborating with Masashi Horiguchi include:

  • Hideharu Tanaka
  • Hiroshi Takyu
  • Hiroki Ueta
  • Ryo Sagisaka

The primary publication venue for Horiguchi's work is the Journal of EMS Medicine.

In 2010, Masashi Horiguchi was awarded the IEEE Fellow distinction for contributions to circuit technologies for high-density low-power memories.

Best Publications

  • Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

    M. Horiguchi;T. Sakata;K. Itoh

  • Semiconductor memory using multiple level storage structure

    Masakazu Aoki;Yoshinobu Nakagome;Masashi Horiguchi;Shinichi Ikenaga

  • Review and future prospects of low-voltage RAM circuits

    Y. Nakagome;M. Horiguchi;T. Kawahara;K. Itoh

  • Semiconductor memory device and defect remedying method thereof

    Kazuhiko Kajigaya;Kazuyuki Miyazawa;Manabu Tsunozaki;Kazuyoshi Oshima

  • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS OPERATION METHOD, ESPECIALLY INCLUDING SERVAL SWITCHING MOSFETS FOR CONTROLLING DRIVING CURRENT SEQUENTLY

    Noda Hiromasa;Aoki Masakazu;Idei Youji;Kajigaya Kazuhiko

  • Memory module including module data wirings available as a memory access data bus

    Seiji Funaba;Yoshinobu Nakagome;Masashi Horiguchi;Yoji Nishio

  • Semiconductor integrated circuits with power reduction mechanism

    Takeshi Sakata;Kiyoo Itoh;Masashi Horiguchi

  • An experimental large-capacity semiconductor file memory using 16-levels/cell storage

    M. Horiguchi;M. Aoki;Y. Nakagome;S. Ikenaga

  • Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)

    T. Kawahara;M. Horiguchi;Y. Kawajiri;G. Kitsukawa

  • The impact of data-line interference noise on DRAM scaling

    Y. Nakagome;M. Aoki;S. Ikenaga;M. Horiguchi

  • Semiconductor device having a reference voltage generating circuit

    Masashi Horiguchi;Masakazu Aoki;Kiyoo Itoh;Yoshinobu Nakagome

  • Subthreshold-current reduction circuits for multi-gigabit DRAM's

    T. Sakata;K. Itoh;M. Horiguchi;M. Aoki

  • A flexible redundancy technique for high-density DRAMs

    M. Horiguchi;J. Etoh;M. Aoki;K. Itoh

  • Nanoscale Memory Repair

    Masashi Horiguchi;Kiyoo Itoh

  • Voltage converter of semiconductor device

    Masashi Horiguchi;Ryoichi Hori;Kiyoo Itoh;Yoshinobu Nakagome

  • Ultra-low voltage nano-scale memories

    Kiyoo Itoh;Masashi Horiguchi;Hitoshi Tanaka

  • A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

    M. Horiguchi;M. Aoki;J. Etoh;H. Tanaka

  • DATA PROCESS SYSTEM

    Kawahara Takayuki;Kawajiri Yoshiki;Akiba Takesada;Horiguchi Masashi

  • Semiconductor IC device having a voltage conversion circuit which generates an internal supply voltage having value compensated for external supply voltage variations

    Kazuhiko Kajigaya;Tetsu Udagawa;Kyoko Ishii;Manabu Tsunozaki

  • 256-Mb DRAM circuit technologies for file applications

    G. Kitsukawa;M. Horiguchi;Y. Kawajiri;T. Kawahara

Frequent Co-Authors

Kiyoo Itoh
Kiyoo Itoh Hitachi (Japan)
Takayuki Kawahara
Takayuki Kawahara Tokyo University of Science
Shinichiro Kimura
Shinichiro Kimura Hitachi (Japan)

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