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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
36
Citations
4761
World Ranking
5392
National Ranking
226

Research.com Recognitions

  • 2017 - IEEE Fellow For leadership in high-density memory technologies for automotive applications

Overview

Hideto Hidaka is affiliated with Renesas Electronics in Japan and has contributed to research primarily in the fields of Electrical and Electronic Engineering and Computer Networks and Communications. Their work spans topics associated with advanced memory technologies and IoT edge computing, reflecting interests in both hardware and system-level innovations.

The main topics covered by Hidaka's research include:

  • Advanced Memory and Neural Computing
  • CCD and CMOS Imaging Sensors
  • IoT and Edge/Fog Computing

Hidaka has authored papers published in respected venues including IEEE Solid-State Circuits Magazine and IEICE Transactions on Electronics. The frequent publication venues are:

  • IEEE Solid-State Circuits Magazine
  • IEICE Transactions on Electronics

Selected recent papers authored or coauthored by Hidaka are:

  • "Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age," 2020, IEICE Transactions on Electronics
  • "Masthead," 2022, IEEE Solid-State Circuits Magazine
  • "Masthead," 2022, IEEE Solid-State Circuits Magazine
  • "Staff List," 2020, IEEE Solid-State Circuits Magazine
  • "Staff list," 2021, IEEE Solid-State Circuits Magazine

Their collaboration network includes frequent coauthors such as Ali Sheikholeslami, Behzad Razavi, Bill Bidermann, Richard Jæger, and Tom Lee, each with numerous joint publications. These collaborations reflect an engaged role within a community of researchers focusing on solid-state circuits and related electronic system topics.

Hidaka's work has been recognized by professional organizations; notably, they were awarded IEEE Fellow status in 2017 for leadership in high-density memory technologies for automotive applications.

Best Publications

  • A built-in self-repair analyzer (CRESTA) for embedded DRAMs

    T. Kawagoe;J. Ohtani;M. Niiro;T. Ooishi

  • Semiconductor memory device allowing high-speed operation of internal data buses

    Hideto Hidaka

  • An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

    K. Suma;T. Tsuruda;H. Hidaka;T. Eimori

  • Semiconductor device with reduced current consumption in standby state

    Tsukasa Ooishi;Takaharu Tsuji;Masatoshi Ishikawa;Hideto Hidaka

  • The Evaluation of Direct Cooling and Heating Desiccant Device Coated with FAM

    Satomi Shimooka;Kazunori Oshima;Hideto Hidaka;Takahiko Takewaki

  • Twisted bit-line architectures for multi-megabit DRAMs

    H. Hidaka;K. Fujishima;Y. Matsuda;M. Asakura

  • Semiconductor memory device containing a cache and an operation method thereof

    Hideto Hidaka;Kazuyasu Fujishima;Yoshio Matsuda;Mikio Asakura

  • Semiconductor memory device having a hierarchical bit line structure with reduced interference noise

    Hideto Hidaka

  • The cache DRAM architecture: a DRAM with an on-chip cache memory

    H. Hidaka;Y. Matsuda;M. Asakura;K. Fujishima

  • Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions

    Hideto Hidaka;Takahiro Tsuruda;Katsuhiro Suma

  • Thin film magnetic storage device

    Hideto Hidaka;秀人 日高

  • A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

    H. Tanaka;M. Aoki;T. Sakata;S. Kimura

  • Dynamic memory device

    Hideshi Miyatake;Kazuyasu Fujishima;Tsutomu Yoshihara;Masaki Kumanoya

  • Bit line structure for semiconductor memory device

    Hideto Hidaka;Kazuyasu Fujishima;Yoshio Matsuda

  • Semiconductor memory device with improved flexible redundancy scheme

    Hideto Hidaka

  • Semiconductor memory device including an SOI

    Hideto Hidaka;Katsuhiro Suma;Takahiro Tsuruda

  • Semiconductor memory device and method of checking same for defect

    Hideto Hidaka;Mikio Asakura;Kiyohiro Furutani;Tetsuo Kato

  • Semiconductor device including an output circuit having a reduced output noise

    Hideto Hidaka;Masakazu Hirose

  • Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block

    Katsumi Dosaka;Masaki Kumanoya;Hideshi Miyatake;Hideto Hidaka

  • Semiconductor memory device having power line arranged in a meshed shape

    Shigeki Tomishima;Mikio Asakura;Kazutami Arimoto;Hideto Hidaka

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