His primary scientific interests are in Operating system, Energy consumption, Embedded system, Efficient energy use and Throughput. The Energy consumption study combines topics in areas such as Single-core, Integrated circuit design, Electronic engineering and Subthreshold conduction. His Single-core course of study focuses on Chip and CPU cache and Multi-core processor.
His Integrated circuit design study combines topics in areas such as Low voltage, Energy conservation, Moore's law and Low-power electronics. His Embedded system research is multidisciplinary, incorporating elements of Discrete event simulation, Computer architecture simulator, Simulation and Power system simulator for engineering. His Server study combines topics from a wide range of disciplines, such as Computer architecture, Service, Deep learning, Artificial intelligence and CUDA.
His primary areas of investigation include Embedded system, Parallel computing, Efficient energy use, Computer hardware and Cache. Ronald G. Dreslinski interconnects Dram, Latency, Random access memory, Power management and Multi-core processor in the investigation of issues within Embedded system. His Speedup and SIMD study in the realm of Parallel computing connects with subjects such as Throughput.
Ronald G. Dreslinski has included themes like Energy consumption, Voltage, Single-core, Subthreshold conduction and Electronic engineering in his Efficient energy use study. His Energy consumption research includes themes of Controller and Energy conservation. His studies deal with areas such as Low voltage and Electrical engineering as well as Electronic engineering.
Ronald G. Dreslinski mainly focuses on Computer architecture, Chip, Parallel computing, RISC-V and CMOS. His study looks at the relationship between Computer architecture and fields such as Dennard scaling, as well as how they intersect with chemical problems. His Chip study integrates concerns from other disciplines, such as Multiplication, Distributed computing and Memory hierarchy.
Parallel computing is often connected to Bottleneck in his work. His RISC-V research is multidisciplinary, incorporating perspectives in Manycore processor, Router, Giga-, Benchmark and Efficient energy use. His CMOS study is associated with Electronic engineering.
Sparse matrix, RISC-V, Multiplication, Matrix multiplication and Massively parallel are his primary areas of study. His research integrates issues of Manycore processor, Giga- and Router in his study of RISC-V. His studies in Router integrate themes in fields like Scalability, Bandwidth and Parallel computing.
His research in Multiplication intersects with topics in Chip, Systolic array and Memory hierarchy, Cache. His Massively parallel study incorporates themes from Computer architecture, High-level synthesis, Reduced instruction set computing, Efficient energy use and Global address space. With his scientific publications, his incorporates both Computer hardware and Throughput.
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The M5 Simulator: Modeling Networked Systems
N.L. Binkert;R.G. Dreslinski;L.R. Hsu;K.T. Lim.
IEEE Micro (2006)
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
R.G. Dreslinski;M. Wieckowski;D. Blaauw;D. Sylvester.
Proceedings of the IEEE (2010)
A survey of multicore processors
G. Blake;R.G. Dreslinski;T. Mudge.
IEEE Signal Processing Magazine (2009)
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor
Taeho Kgil;Shaun D'Souza;Ali Saidi;Nathan Binkert.
architectural support for programming languages and operating systems (2006)
Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers
Johann Hauswald;Michael A. Laurenzano;Yunqi Zhang;Cheng Li.
architectural support for programming languages and operating systems (2015)
Full-system analysis and characterization of interactive smartphone applications
Anthony Gutierrez;Ronald G. Dreslinski;Thomas F. Wenisch;Trevor Mudge.
ieee international symposium on workload characterization (2011)
Composite Cores: Pushing Heterogeneity Into a Core
Andrew Lukefahr;Shruti Padmanabha;Reetuparna Das;Faissal M. Sleiman.
international symposium on microarchitecture (2012)
Catnap: energy proportional multiple network-on-chip
Reetuparna Das;Satish Narayanasamy;Sudhir K. Satpathy;Ronald G. Dreslinski.
international symposium on computer architecture (2013)
DjiNN and Tonic: DNN as a service and its implications for future warehouse scale computers
Johann Hauswald;Yiping Kang;Michael A. Laurenzano;Quan Chen.
international symposium on computer architecture (2015)
Sources of Error in Full-System Simulation
Anthony Gutierrez;Joseph Pusdesris;Ronald G. Dreslinski;Trevor N. Mudge.
international symposium on performance analysis of systems and software (2014)
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