World's Best Scientists 2026 revealed!
Jean-Luc Autran

Jean-Luc Autran

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
32
Citations
4700
World Ranking
6272
National Ranking
131

Best Publications

  • Tantalum pentoxide (Ta2O5) thin films for advanced dielectric applications

    Unknown

  • Modeling and Simulation of Single-Event Effects in Digital Devices and ICs

    D. Munteanu;J.-L. Autran

  • Technology downscaling worsening radiation effects in bulk: SOI to the rescue

    Philippe Roche;Jean-Luc Autran;Gilles Gasiot;Daniela Munteanu

  • Influence of band-structure on electron ballistic transport in silicon nanowire MOSFET's: an atomistic study

    K. Nehari;N. Cavassilas;J.L. Autran;M. Bescond

  • On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs

    Unknown

  • Quantum Short-channel Compact Modelling of Drain-Current in Double-Gate MOSFET

    Daniela Munteanu;Jean-Luc Autran;Xavier Loussier;Samuel Harrison

  • Interfacial hardness enhancement in deuterium annealed 0.25 μm channel metal oxide semiconductor transistors

    Unknown

  • Single Event Upset and Multiple Cell Upset Modeling in Commercial Bulk 65-nm CMOS SRAMs and Flip-Flops

    Slawosz Uznanski;Gilles Gasiot;Philippe Roche;Clement Tavernier

  • Fabrication and characterization of Si-MOSFET's with PECVD amorphous Ta 2 O 5 gate insulator

    Unknown

  • Electrical properties of Ta2O5 films obtained by plasma enhanced chemical vapor deposition using a TaF5 source

    R.A.B. Devine;Laurent Vallier;Jean-Luc Autran;P. Paillet

  • Frequency characterization and modeling of interface traps in HfSixOy/HfO2 gate dielectric stack from a capacitance point-of-view

    Pascal Masson;Jean-Luc Autran;Michel Houssa;Xavier Garros

  • Altitude and Underground Real-Time SER Characterization of CMOS 65 nm SRAM

    J.L. Autran;P. Roche;S. Sauze;G. Gasiot

  • 3D quantum modeling and simulation of multiple-gate nanowire MOSFETs

    M. Bescond;K. Nehari;J.L. Autran;N. Cavassilas

  • Heavy Ion Testing and 3-D Simulations of Multiple Cell Upset in 65 nm Standard SRAMs

    D. Giot;P. Roche;G. Gasiot;J.-L. Autran

  • Highly performant double gate MOSFET realized with SON process

    S. Harrison;P. Coronel;F. Leverd;R. Cerutti

  • Soft Errors : From Particles to Circuits

    Daniela Munteanu

  • Experimental Investigation on the Quasi-Ballistic Transport: Part I—Determination of a New Backscattering Coefficient Extraction Methodology

    V. Barral;T. Poiroux;J. Saint-Martin;D. Munteanu

  • Experimental Investigation on the Quasi-Ballistic Transport: Part II—Backscattering Coefficient Extraction and Link With the Mobility

    V. Barral;T. Poiroux;D. Munteanu;J.-L. Autran

  • Full-band study of current across silicon nanowire transistors

    Unknown

  • Atomic-scale modeling of double-gate MOSFETs using a tight-binding Green’s function formalism

    M Bescond;Jean-Luc Autran;Daniela Munteanu;M Lannoo

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