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Mitsumasa Koyanagi

Mitsumasa Koyanagi

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
40
Citations
8214
World Ranking
4430
National Ranking
169

Overview

Mitsumasa Koyanagi is affiliated with Tohoku University in Japan, specializing in research within the field of engineering, with a focus on electrical and electronic engineering. Their work predominantly covers topics in 3D IC and TSV (through-silicon via) technologies, electronic packaging and soldering technologies, and the synthesis and properties of polymers.

Their recent publications include the following papers:

  • "Comprehensive Study on Advanced Chip on Wafer Hybrid Bonding with Copper/Polyimide Systems" (2022), published in 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
  • "Cu-SiO2 Hybrid Bonding Yield Enhancement Through Cu Grain Enlargement" (2022), published in 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
  • "On-wafer thermomechanical characterization of a thin film polyimide formed by vapor deposition polymerization for through-silicon via applications: Comparison to plasma-enhanced chemical vapor deposition SiO2" (2020), published in Journal of Polymer Science
  • "High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications" (2020), published in Japanese Journal of Applied Physics
  • "Cyclic reservoir neural network circuit for 3D IC implementation" (2021), published in Nonlinear Theory and Its Applications IEICE

Frequent co-authors of Mitsumasa Koyanagi include:

  • Takafumi Fukushima
  • M. Murugesan
  • Tomoaki Shibata
  • K. Mori
  • Hiroyuki Hashimoto

Common venues where this research is published include:

  • 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
  • Journal of Polymer Science
  • Japanese Journal of Applied Physics
  • Nonlinear Theory and Its Applications IEICE
  • IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Their research spans several specialized fields including electrical and electronic engineering, polymers and plastics, electronic, optical and magnetic materials, biomedical engineering, and atomic and molecular physics and optics.

Key topics addressed in their work are:

  • 3D IC and TSV technologies
  • Electronic Packaging and Soldering Technologies
  • Synthesis and properties of polymers
  • Copper Interconnects and Reliability
  • Nanofabrication and Lithography Techniques
  • Semiconductor materials and devices
  • Semiconductor materials and interfaces

Best Publications

  • Future system-on-silicon LSI chips

    M. Koyanagi;H. Kurino;Kang Wook Lee;K. Sakuma

  • High-Density Through Silicon Vias for 3-D LSIs

    M. Koyanagi;T. Fukushima;T. Tanaka

  • Three-dimensional shared memory fabricated using wafer stacking technology

    K.W. Lee;T. Nakamura;T. Ono;Y. Yamada

  • Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

    M. Koyanagi;T. Nakamura;Y. Yamada;H. Kikuchi

  • Three-dimensional integration technology and integrated systems

    Mitsumasa Koyanagi;Takafumi Fukushima;Tetsu Tanaka

  • Neuromorphic vision chip fabricated using three-dimensional integration technology

    M. Koyanagi;Y. Nakagawa;Kang-Wook Lee;T. Nakamura

  • Hot-electron-induced punchthrough (HEIP) effect in submicrometer PMOSFET's

    M. Koyanagi;A.G. Lewis;R.A. Martin;Tiao-Yuan Huang

  • Intelligent image sensor chip with three dimensional structure

    H. Kurino;K.W. Lee;T. Nakamura;K. Sakuma

  • New three-dimensional integration technology using self-assembly technique

    T. Fukushima;Y. Yamada;H. Kikuchi;M. Koyanagi

  • A novel submicron LDD transistor with inverse-T gate structure

    Tiao-yuan Huang;W.W. Yao;R.A. Martin;A.G. Lewis

  • New non-volatile memory with extremely high density metal nano-dots

    M. Takata;S. Kondoh;T. Sakaguchi;H. Choi

  • New Three-Dimensional Wafer Bonding Technology Using the Adhesive Injection Method.

    Takuji Matsumoto;Masakazu Satoh;Katsuyuki Sakuma;Hiroyuki Kurino

  • New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique

    T. Fukushima;H. Kikuchi;Y. Yamada;T. Konno

  • Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

    Kang-Wook Lee;A Noriki;K Kiyoyama;T Fukushima

  • Novel high density, stacked capacitor MOS RAM

    M. Koyanagi;H. Sunami;N. Hashimoto;M. Ashikawa

  • Surface tension-driven chip self-assembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits

    T. Fukushima;E. Iwata;T. Konno;J.-C. Bea

  • Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias

    M. Murugesan;H. Kino;H. Nohira;J.C. Bea

  • Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs

    Hirokazu Kikuchi;Yusuke Yamada;Atif Mossad Ali;Jun Liang

  • New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration

    Takafumi Fukushima;Yusuke Yamada;Hirokazu Kikuchi;Mitsumasa Koyanagi

  • Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip.

    Kang Wook Lee;Tomonori Nakamura;Katsuyuki Sakuma;Ki Tae Park

Frequent Co-Authors

Masanobu Miyao
Masanobu Miyao Kyushu University
Kazuhiro Hane
Kazuhiro Hane Tohoku University
Ki-Tae Park
Ki-Tae Park Samsung (South Korea)
Seiichi Miyazaki
Seiichi Miyazaki Hiroshima University
Yutaka S. Sato
Yutaka S. Sato Tohoku University
Seiji Samukawa
Seiji Samukawa Tohoku University
Mikihiko Oogane
Mikihiko Oogane Tohoku University
Hideo Ohno
Hideo Ohno Tohoku University
Teruo Ono
Teruo Ono Kyoto University
Shoji Ikeda
Shoji Ikeda Tohoku University

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