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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
31
Citations
7121
World Ranking
6455
National Ranking
2114

Overview

Ken Mai is affiliated with Carnegie Mellon University in the United States. The primary fields of study for their research include Engineering and Computer Science, with further specialization in subfields such as Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Aerospace Engineering, Hardware and Architecture, and Cellular and Molecular Neuroscience.

Their research spans multiple main topics, which include Integrated Circuits and Semiconductor Failure Analysis, Robotics and Sensor-Based Localization, Advanced Vision and Imaging, Advanced Image and Video Retrieval Techniques, Physical Unclonable Functions (PUFs) and Hardware Security, Neuroscience and Neural Engineering, and Force Microscopy Techniques and Applications.

Ken Mai has contributed to several recent papers covering a variety of subjects and venues:

  • Split-Chip Design to Prevent IP Reverse Engineering, 2020, IEEE Design and Test
  • Towards Specialized Hardware for Learning-based Visual Odometry on the Edge, 2022, 2022 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)
  • In Situ Observation of Circuit Behavior Using Pump-Probe Laser Voltage Probe Technique, 2024, IEEE Transactions on Nuclear Science
  • Multi-heat keypoint incorporation in deep learning model to tropical cyclone centering and intensity classifying from geostationary satellite images, 2025, Scientific Reports
  • Microwave-tailored S-scheme MOF@MOF heterojunctions: Synergistic dual-charge transfer and polarization enhancement toward efficient antibiotic degradation, 2025, Chemical Engineering Journal

Ken Mai has collaborated with various frequent coauthors, including Siyuan Chen, Samuel Pagliarini, Joseph Sweeney, R. D. Blanton, and Larry Pileggi.

Publication venues where Ken Mai's work has appeared include:

  • 2022 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)
  • IEEE Design and Test
  • IEEE Transactions on Nuclear Science
  • Scientific Reports
  • Chemical Engineering Journal

Best Publications

  • The future of wires

    R. Ho;K.W. Mai;M.A. Horowitz

  • Error patterns in MLC NAND flash memory: measurement, characterization, and analysis

    Yu Cai;Erich F. Haratsch;Onur Mutlu;Ken Mai

  • Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

    Jangwoo Kim;Nikos Hardavellas;Ken Mai;Babak Falsafi

  • Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

    Eric S. Chung;Peter A. Milder;James C. Hoe;Ken Mai

  • Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

    Yu Cai;Yixin Luo;Erich F. Haratsch;Ken Mai

  • Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling

    Yu Cai;Erich F. Haratsch;Onur Mutlu;Ken Mai

  • Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime

    Yu Cai;Gulay Yalcin;Onur Mutlu;Erich F. Haratsch

  • Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

    B.H. Calhoun;Yu Cao;Xin Li;Ken Mai

  • Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

    Yu Cai;Onur Mutlu;Erich F. Haratsch;Ken Mai

  • CoRAM: an in-fabric memory architecture for FPGA-based computing

    Eric S. Chung;James C. Hoe;Ken Mai

  • Low-power SRAM design using half-swing pulse-mode techniques

    K.W. Mai;T. Mori;B.S. Amrutur;R. Ho

  • Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques

    Yu Cai;Saugata Ghose;Yixin Luo;Yixin Luo;Ken Mai

  • Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

    Unknown

  • Efficient on-chip global interconnects

    R. Ho;K. Mai;M. Horowitz

  • ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs

    Eric S. Chung;Michael K. Papamichael;Eriko Nurvitadhi;James C. Hoe

  • An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

    Mudit Bhargava;Ken Mai

  • Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS

    Mudit Bhargava;Cagla Cakir;Ken Mai

  • Applications of on-chip samplers for test and measurement of integrated circuits

    Ron Ho;B. Amrutur;Ken Mai;B. Wilburn

  • Neighbor-cell assisted error correction for MLC NAND flash memories

    Yu Cai;Gulay Yalcin;Onur Mutlu;Erich F. Haratsch

  • A high reliability PUF using hot carrier injection based response reinforcement

    Mudit Bhargava;Ken Mai

  • An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

    Unknown

  • Snafu: an ultra-low-power, energy-minimal CGRA-generation framework and architecture

    Graham Gobieski;Ahmet Oguz Atli;Kenneth Mai;Brandon Lucia

  • Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses

    Mudit Bhargava;Cagla Cakir;Ken Mai

  • Read Disturb Errors in MLC NAND Flash Memory

    Yu Cai;Yixin Luo;Saugata Ghose;Erich F. Haratsch

  • Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS : Small transistors necessitate big changes, in the way digital circuits are modeled and optimized for manufacturability, and new strategies for logic, memory, clocking and power distribution

    Benton H. Calhoun;Yu Cao;Xin Li;Ken Mai

Frequent Co-Authors

Mark Horowitz
Mark Horowitz Stanford University
Larry Pileggi
Larry Pileggi Carnegie Mellon University
Benton H. Calhoun
Benton H. Calhoun University of Virginia
Farinaz Koushanfar
Farinaz Koushanfar University of California, San Diego
Elad Alon
Elad Alon University of California, Berkeley
Radu Marculescu
Radu Marculescu The University of Texas at Austin
Ramesh Karri
Ramesh Karri New York University
Yu Cao
Yu Cao University of Minnesota
Rob A. Rutenbar
Rob A. Rutenbar University of Pittsburgh
Kenneth L. Shepard
Kenneth L. Shepard Columbia University

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