World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
33
Citations
4751
World Ranking
6051
National Ranking
124

Best Publications

  • Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

    S. Barraud;M. Berthome;R. Coquand;M. Casse

  • Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

    O. Faynot;F. Andrieu;O. Weber;C. Fenouillet-Beranger

  • Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

    M. Casse;L. Thevenod;B. Guillaumot;L. Tosti

  • Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening

    Unknown

  • FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

    C. Fenouillet-Beranger;S. Denorme;P. Perreau;C. Buj

  • Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

    S. Barraud;R. Coquand;M. Casse;M. Koyama

  • Bonded planar double-metal-gate NMOS transistors down to 10 nm

    M. Vinet;T. Poiroux;J. Widiez;J. Lolivier

  • 3DVLSI with CoolCube process: An alternative path to scaling

    P. Batude;C. Fenouillet-Beranger;L. Pasini;V. Lu

  • Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

    F. Andrieu;O. Weber;J. Mazurier;O. Thomas

  • Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

    R. Coquand;M. Casse;S. Barraud;D. Cooper

  • 7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

    S. Barraud;B. Previtali;C. Vizioz;J.-M. Hartmann

  • Strained tunnel FETs with record I ON : first demonstration of ETSOI TFETs with SiGe channel and RSD

    A. Villalon;C. Le Royer;M. Casse;D. Cooper

  • Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric

    F. Lime;K. Oshima;M. Cassé;G. Ghibaudo

  • Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

    R. Coquand;S. Barraud;M. Casse;P. Leroux

  • Efficient multi-V T FDSOI technology with UTBOX for low power circuit design

    C. Fenouillet-Beranger;O. Thomas;P. Perreau;J-P. Noel

  • Spectroscopic charge pumping in Si nanowire transistors with a high-κ/metal gate

    M. Cassé;K. Tachi;S. Thiele;T. Ernst

  • Gate-induced floating-body effect in fully-depleted SOI MOSFETs with tunneling oxide and back-gate biasing

    M. Cassé;J. Pretet;J. Pretet;S. Cristoloveanu;T. Poiroux

  • Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

    F. Andrieu;T. Ernst;F. Lime;F. Rochette

  • Self-Heating Effect in FDSOI Transistors Down to Cryogenic Operation at 4.2 K

    K. Triantopoulos;M. Casse;S. Barraud;S. Haendler

  • Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing

    B. Cardoso Paz;L. Le Guevel;M. Casse;G. Billiot

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