M. Casse

Best Publications

• Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

  S. Barraud;M. Berthome;R. Coquand;M. Casse

  269
  Citations

• Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

  O. Faynot;F. Andrieu;O. Weber;C. Fenouillet-Beranger

  237
  Citations

• Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

  M. Casse;L. Thevenod;B. Guillaumot;L. Tosti

  190
  Citations

• Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening

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  173
  Citations

• FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

  C. Fenouillet-Beranger;S. Denorme;P. Perreau;C. Buj

  167
  Citations

• Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

  S. Barraud;R. Coquand;M. Casse;M. Koyama

  166
  Citations

• Bonded planar double-metal-gate NMOS transistors down to 10 nm

  M. Vinet;T. Poiroux;J. Widiez;J. Lolivier

  153
  Citations

• 3DVLSI with CoolCube process: An alternative path to scaling

  P. Batude;C. Fenouillet-Beranger;L. Pasini;V. Lu

  150
  Citations

• Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

  F. Andrieu;O. Weber;J. Mazurier;O. Thomas

  111
  Citations

• Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

  R. Coquand;M. Casse;S. Barraud;D. Cooper

  89
  Citations

• 7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

  S. Barraud;B. Previtali;C. Vizioz;J.-M. Hartmann

  87
  Citations

• Strained tunnel FETs with record I ON : first demonstration of ETSOI TFETs with SiGe channel and RSD

  A. Villalon;C. Le Royer;M. Casse;D. Cooper

  85
  Citations

• Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric

  F. Lime;K. Oshima;M. Cassé;G. Ghibaudo

  81
  Citations

• Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

  R. Coquand;S. Barraud;M. Casse;P. Leroux

  74
  Citations

• Efficient multi-V T FDSOI technology with UTBOX for low power circuit design

  C. Fenouillet-Beranger;O. Thomas;P. Perreau;J-P. Noel

  73
  Citations

• Spectroscopic charge pumping in Si nanowire transistors with a high-κ/metal gate

  M. Cassé;K. Tachi;S. Thiele;T. Ernst

  71
  Citations

• Gate-induced floating-body effect in fully-depleted SOI MOSFETs with tunneling oxide and back-gate biasing

  M. Cassé;J. Pretet;J. Pretet;S. Cristoloveanu;T. Poiroux

  66
  Citations

• Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

  F. Andrieu;T. Ernst;F. Lime;F. Rochette

  66
  Citations

• Self-Heating Effect in FDSOI Transistors Down to Cryogenic Operation at 4.2 K

  K. Triantopoulos;M. Casse;S. Barraud;S. Haendler

  65
  Citations

• Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing

  B. Cardoso Paz;L. Le Guevel;M. Casse;G. Billiot

  52
  Citations