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Tetsu Tanaka

Tetsu Tanaka

D-Index & Metrics

Engineering and Technology

D-Index
34
Citations
7304
World Ranking
9123
National Ranking
201

Overview

Tetsu Tanaka is affiliated with Tohoku University in Japan. Their research primarily focuses on the fields of engineering and neuroscience, with significant contributions in electrical and electronic engineering as well as cellular and molecular neuroscience.

Their body of work covers a range of interdisciplinary subfields including biomedical engineering, materials chemistry, and cognitive neuroscience. Tanaka's research intersects topics such as neuroscience and neural engineering, photoreceptor and optogenetics research, 3D integrated circuits and through-silicon via technologies, advanced memory and neural computing, electronic packaging and soldering technologies, advanced sensor and energy harvesting materials, and imaging using CCD and CMOS sensors.

Frequent coauthors in their publications include Takafumi Fukushima, Hisashi Kino, Yuki Susumago, Bang Du, and N. Katayama, indicating collaborative efforts across these areas.

Tanaka has contributed articles to several publication venues. Notably, these include:

  • Japanese Journal of Applied Physics
  • Extended Abstracts of the 2020 International Conference on Solid State Devices and Materials
  • Applied Physics Express
  • Journal of Polymer Science
  • IEEE Electron Device Letters

Their recent papers include:

  • On-wafer thermomechanical characterization of a thin film polyimide formed by vapor deposition polymerization for through-silicon via applications: Comparison to plasma-enhanced chemical vapor deposition SiO2, 2020, Journal of Polymer Science
  • Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED, 2023, IEEE Electron Device Letters
  • Room-Temperature Cu Direct Bonding Technology Enabling 3D Integration with Micro-LEDs, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
  • Enhancement of carrier mobility in metal-oxide semiconductor field-effect transistors using negative thermal expansion gate electrodes, 2022, Applied Physics Express
  • Significant Die-Shift Reduction and μLED Integration Based on Die-First Fan-Out Wafer-Level Packaging for Flexible Hybrid Electronics, 2020, IEEE Transactions on Components Packaging and Manufacturing Technology

Best Publications

  • Scaling theory for double-gate SOI MOSFET's

    K. Suzuki;T. Tanaka;Y. Tosaka;H. Horie

  • Efficacy of catheter-based renal denervation in the absence of antihypertensive medications (SPYRAL HTN-OFF MED Pivotal): a multicentre, randomised, sham-controlled trial

    Michael Böhm;Kazuomi Kario;David E. Kandzari;Felix Mahfoud;Felix Mahfoud

  • High-Density Through Silicon Vias for 3-D LSIs

    M. Koyanagi;T. Fukushima;T. Tanaka

  • A comparative study of advanced MOSFET concepts

    C.H. Wann;K. Noda;K. Noda;T. Tanaka;M. Yoshida;M. Yoshida

  • Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

    M. Koyanagi;T. Nakamura;Y. Yamada;H. Kikuchi

  • A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory

    E. Yoshida;T. Tanaka

  • A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory

    E. Yoshida;T. Tanaka

  • Three-dimensional integration technology and integrated systems

    Mitsumasa Koyanagi;Takafumi Fukushima;Tetsu Tanaka

  • Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SOI to double-gate FinDRAM

    T. Tanaka;E. Yoshida;T. Miyashita

  • Radio relay system, radio relay apparatus, and radio relay method

    Hiromasa Fujii;Hirohito Suda;Tetsu Tanaka

  • New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique

    T. Fukushima;H. Kikuchi;Y. Yamada;T. Konno

  • Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

    Kang-Wook Lee;A Noriki;K Kiyoyama;T Fukushima

  • Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's

    T. Tanaka;K. Suzuki;H. Horie;T. Sugii

  • Surface tension-driven chip self-assembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits

    T. Fukushima;E. Iwata;T. Konno;J.-C. Bea

  • Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias

    M. Murugesan;H. Kino;H. Nohira;J.C. Bea

  • Wireless relay system, apparatus and method

    Fujii Hiromasa;Suda Hirohito;Tanaka Tetsu

  • Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs

    Hirokazu Kikuchi;Yusuke Yamada;Atif Mossad Ali;Jun Liang

  • Analysis of p/sup +/ poly Si double-gate thin-film SOI MOSFETs

    T. Tanaka;H. Horie;S. Ando;S. Hijiya

  • A study of highly scalable DG-FinDRAM

    E. Yoshida;T. Miyashita;T. Tanaka

  • Analytical surface potential expression for thin-film double-gate SOI MOSFETs

    Kunihiro Suzuki;Tetsu Tanaka;Yoshiharu Tosaka;Hiroshi Horie

Frequent Co-Authors

Mitsumasa Koyanagi
Mitsumasa Koyanagi Tohoku University
Hajime Mushiake
Hajime Mushiake Tohoku University
Hideki Hashimoto
Hideki Hashimoto Chuo University
Makoto Tamai
Makoto Tamai Tohoku University
Masanobu Miyao
Masanobu Miyao Kyushu University
Yutaka S. Sato
Yutaka S. Sato Tohoku University
Malte Kelm
Malte Kelm Heinrich Heine University Düsseldorf
Mikihiko Oogane
Mikihiko Oogane Tohoku University
Hideo Ohno
Hideo Ohno Tohoku University
Stephan Baldus
Stephan Baldus University of Cologne

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