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Darrell Rinerson

Darrell Rinerson

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
39
Citations
4435
World Ranking
4785
National Ranking
77

Overview

Darrell Rinerson is affiliated with Memoria Technology, based in Switzerland. Their work and professional activities are connected to this organization, indicating involvement in technology-related research or applications.

There are no recorded recent papers, frequent co-authors, or recurring publication venues associated with Darrell Rinerson. This absence of data suggests limited publicly indexed publication activity or collaborative networks available through current sources.

No book publications by Darrell Rinerson have been documented, nor are there any specified main fields or subfields of study linked to their work. Similarly, main topics of research coverage have not been identified in the available data.

There is no record of awards attributed to Darrell Rinerson, and they are currently living.

Best Publications

  • Cross point memory array using multiple thin films

    Darrell Rinerson;Steven W. Longcor;Edmond R. Ward;Steve Kuo-Ren Hsia

  • Memory using mixed valence conductive oxides

    Darrell Rinerson;Christophe J. Chevallier;Wayne Kinney;Roy Lambertson

  • Adaptive programming technique for a re-writable conductive memory device

    Darrell Rinerson;Christophe J. Chevallier

  • Conductive memory device with conductive oxide electrodes

    Darrell Rinerson;Steven W. Longcor;Steve Kuo-Ren Hsia;Wayne Kinney

  • Discharge of conductive array lines in fast memory

    Christophe Chevallier;Darrell Rinerson

  • Multiple modes of operation in a cross point array

    Darrell Rinerson;Christophe J. Chevallier;Steven W. Longcor;Edmond R. Ward

  • Tri layer metal oxide rewritable non volatile two terminal memory element

    Darrell Rinerson;Christophe Chevallier;Wayne Kinney;Edmond Ward

  • Multi-layer conductive memory device

    Wayne Kinney;Steven W. Longcor;Darrell Rinerson;Steve Kuo-Ren Hsia

  • Memory array of a non-volatile RAM

    Darrell Rinerson;Christophe J. Chevallier

  • Line drivers that fit within a specified line pitch

    Darrell Rinerson;Christophe J. Chevallier

  • Non-volatile memory with a single transistor and resistive memory element

    Darrell Rinerson;Christophe J. Chevallier

  • Providing a reference voltage to a cross point memory array

    Darrell Rinerson;Christophe J. Chevallier

  • High-density NVRAM

    Darrell Rinerson;Steven W. Longcor;Edmond R. Ward;Steve Kuo-Ren Hsia

  • Memory element with a reactive metal layer

    Christophe J. Chevallier;Steve Kuo-Ren Hsia;Wayne Kinney;Steven Longcor

  • Resistive memory device with a treated interface

    Darrell Rinerson;Wayne Kinney;John E. Sanchez;Steven W. Longcor

  • 2-terminal trapped charge memory device with voltage switchable multi-level resistance

    Darrell Rinerson;Wayne Kinney;Steven W. Longcor;Edmond R. Ward

  • Two terminal memory array having reference cells

    Darrell Rinerson;Christophe J. Chevallier;Steven W. Longcor

  • Memory element having islands

    Darrell Rinerson;Christophe Chevallier;Philip Swab;Steve Hsia

  • Multi-resistive state material that uses dopants

    Darrell Rinerson;Wayne Kinney;Christophe J. Chevallier;Steven W. Longcor

  • Threshold device for a memory array

    Darrell Rinerson;Julie Casperson Brewer;Christophe J. Chevallier;Wayne Kinney

  • A 0.13µm 64Mb multi-layered conductive metal-oxide memory

    Christophe J Chevallier;Chang Hua Siau;Seow Fong Lim;Sri Rama Namala

Frequent Co-Authors

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