Carl Sechen

Best Publications

• The TimberWolf placement and routing package

  C. Sechen;A. Sangiovanni-Vincentelli

  740
  Citations

• TimberWolf3.2: A New Standard Cell Placement and Global Routing Package

  Carl Sechen;Alberto Sangiovanni-Vincentelli

  314
  Citations

• VLSI Placement and Global Routing Using Simulated Annealing

  Unknown

  243
  Citations

• Timing driven placement for large standard cell circuits

  Unknown

  174
  Citations

• INVITED: Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project

  Tutu Ajayi;Vidya A. Chhabria;Mateus Fogaca;Soheil Hashemi

  158
  Citations

• Efficient and effective placement for very large circuits

  Unknown

  113
  Citations

• A unified approach to the approximate symbolic analysis of large analog integrated circuits

  Unknown

  109
  Citations

• New algorithms for the placement and routing of macro cells

  Unknown

  108
  Citations

• TimberWolf3.2: A New Standard Cell Placement and Global Routing Package

  Unknown

  96
  Citations

• Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

  Unknown

  89
  Citations

• A new global router for row-based layout

  Unknown

  87
  Citations

• The charge‐flow transistor: A new MOS device

  S. D. Senturia;C. M. Sechen;J. A. Wishneusky

  73
  Citations

• Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step

  Unknown

  73
  Citations

• A MEMS-Assisted Temperature Sensor With 20- $\mu ext{K}$ Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2

  Meisam Heidarpour Roshan;Samira Zaliasl;Kimo Joo;Kamran Souri

  61
  Citations

• Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

  Unknown

  61
  Citations

• DC small signal symbolic analysis of large analog integrated circuits

  Unknown

  56
  Citations

• Efficient and effective placement for very large circuits

  Unknown

  52
  Citations

• An improved objective function for mincut circuit partitioning

  Unknown

  52
  Citations

• Clock-delayed domino for adder and combinational logic design

  Unknown

  45
  Citations

• Timing and crosstalk driven area routing

  Unknown

  44
  Citations