IEEE Electronic Components and Technology Conference (ECTC)

Highly rated abstracts are accepted for presentation at the ECTC conference. It is important
that authors identify the subcommittees whose topic areas best fit their abstracts. Abstracts
should include original and previously unpublished, non-confidential, and non-commercial
information on new developments, technology, and knowledge in the areas including, but not
limited to, those given below for each technical subcommittee.
Applied Reliability: Reliability of 2D, 2.5D, Si-bridge, 3D, chiplets, SiP, WLCSP, FOWLP,
FOPLP & heterogeneous integration; Interconnect reliability in micro-bump, micro-pillar, Cupillar, TSV, TGV, RDL, HDI, stacked-die, hybrid-bond, flip chip & wire bonded packages; Novel
reliability test methods, life models, FA techniques & materials characterization; Component
and board level reliability in computing, HPC, mobile, networking, automotive, power
electronics, harsh/hi-temp environments, IoT, sensors, AI, autonomous vehicles, medical,
wearable electronics, LEDs, displays & memory.
Assembly and Manufacturing Technology: Assembly and manufacturing challenges
for new markets; Die bonding methods and processes; embedded packaging and modules;
Wafer level process/materials technologies; Die and package singulation manufacturing;
New & next generation substrates; Smart factory/manufacturing; Design for Manufacturing;
Assembly related test/yield hardware development; Integrating advanced thermal solutions
in manufacturing: Design/performance, integrating solutions, thermal materials, low stress/
high thermal; Process advancements/yield enhancements: Cost of inspection, sampling,
metrology, new processes for fine RDL, small via fabrication, transfer/compression/injection
mold; Heterogeneous integration and process: chiplets, 3D stacking, bridge technology, large
body, warpage management; Shielding/protection technologies and manufacturing and market
requirements.
Emerging Technologies: Emerging, novel and unique packaging and material technologies
for: Soft and intelligent packaging; Flexible/stretchable hybrid electronics; Implantable biosensors
and bioelectronics; Bio-resorbable packaging; Extreme harsh environment; Nanomanufacturing;
Paper sensors/electronics pop-up/origami; MEMS & NEMS; Close-To-Motor high-voltage
power electronics; Packaging for wide band gap devices; Anti-tamper, cryptography; Additive
manufacturing; Packaging for quantum computing and electro-optical integration; Recyclable
and sustainable electronics packaging; AI, ML and computer vision for packaging; Point-of-care
diagnostic packaging; Space hardened packaging; Green and sustainable electronics; Net zero
strategy/technology.
Interconnections: Interconnection Technology and Processing: Hybrid/direct Cu bonding,
fan-out, panel-level, chiplets, SiP, flip-chip, 2.5D/3D, Si/glass/organic interposers, TSV, microbump, Cu pillar, wirebonding, thermo-compression bonding, fine-pitch/multi-layer RDL,
printable interconnects, flexible substrates, photonic interconnects, quantum interconnects;
Interconnection material, characterization and reliability; Conductive/non-conductive adhesives,
low temperature solder, underfill, molding compounds, thermal interface materials, thermal/
mechanical/electrical tests and reliability; Interconnection physical co-design and architectures
for emerging applications- HPC, mobile, 5G, IoT, power and rugged electronics, medical and
health, automotive, aerospace, flexible hybrid electronics, micro-LED display.
Materials & Processing: Wafer & panel level packaging materials; Materials for harsh
environments; Packaging substrates; Flexible, stretchable, & wearable electronics; Wafer bond/
debond materials; TSV; Emerging electronic materials & processes; Novel solder metallurgies;
Dielectrics and underfills; Molding compounds; Thermal interface materials; Advanced
wirebonding, conductive adhesives
Packaging Technologies: Architectures, chiplets, and applications for 2.5 & 3D, TSV &
interposer; Advanced flip-chip, SiP, CSP, PoP, MEMS, sensors & IoT; Automotive & power
electronics; bio, medical, flexible & wearable packaging; Embedded & advanced substrates; Fanout, wafer & panel level processes; Heterogeneous integration.
Photonics: Assembly and packaging for all applications that leverage photonics components
and circuits. Packaging of Photonics Integrated Circuits for telecom, datacom, and 5G; Copackaged and near-packaged optics; Heterogeneous integration; Artificial intelligence; quantum
systems such as processors, sensors, and networks; Medical devices; Automotive/LIDAR;
Aerospace, defense, and cryogenic/harsh environment; RF/MW photonics; Free-space optics;
AR/VR; WDM, and high power lasers; Micro-LEDs and 3D light-field displays; Imaging and
environmental sensors; New materials, connectors; EDA tools, and test methods/equipment.
RF, High-Speed Components & Systems: 5G/6G, IoT, cloud computing, autonomous
vehicles, AI/machine learning; Antennas, radars, sensors, power transfer, EM shielding, wired/
wireless communications, RF to THz; Electrical and multi-physics modeling, simulation and
characterization of interconnects, components, modules, and heterogeneous integration;
Signal/power integrity, and chip/package/board co-design.
Thermal/Mechanical Simulation & Characterization: Thermal/mechanical simulation
and characterization at component, board, and system levels for all packaging technologies:
Reliability-related modeling including fracture mechanics, fatigue, electromigration, warpage,
delamination, moisture, drop, shock and vibration, and modeling for harsh environments
(thermal, chemical, etc.); Material constitutive relations; Chip-package interaction for
heterogeneous integration, wafer fabrication and package assembly process related modeling;
Novel modeling techniques including multi-scale physics, co-design approaches; Quantum
computing; Measurement methodologies, characterization and correlations, model order
reduction, sensitivity analysis, optimization, statistical analysis; Application of artificial intelligence
on modeling, characterization, digital twin; Simulations for virtual release.
Interactive Presentations: Highly encouraged at ECTC, presenters and attendees often
communicate more efficiently here than in oral presentations. Abstracts can relate to any
electronics packaging topic. Interactive presentation session papers are published and archived
in equal merit with the other ECTC papers.
You are invited to submit an abstract between 250 and 750 words with 1 table (or figure)
that describes the novelty, scope, content, and key points of your proposed manuscript via the
website at www.ectc.net. Please start your abstract with a first paragraph of no more than
50 words to clearly highlight and summarize the novelty of your work.