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Computer Science

D-Index
33
Citations
5827
World Ranking
12516
National Ranking
795

Overview

Simon W. Moore is affiliated with the University of Cambridge in the United Kingdom. Their research spans primarily the fields of Computer Science and Engineering, with significant contributions in subfields such as Artificial Intelligence, Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, and Signal Processing.

The main topics covered in their body of work include Security and Verification in Computing, Parallel Computing and Optimization Techniques, Radiation Effects in Electronics, Cryptographic Implementations and Security, Distributed Systems and Fault Tolerance, Advanced Malware Detection Techniques, and Advanced Memory and Neural Computing.

Their recent publications reflect a focus on capability-based computer architecture and security mechanisms. Selected papers include:

  • "Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 6)" (2021) published in CL Technical Reports
  • "The Arm Morello Evaluation Platform-Validating CHERI-Based Security in a High-Performance System" (2023) published in IEEE Micro
  • "Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture" (2021) published in CL Technical Reports
  • "CHERI C/C++ Programming Guide" (2021) published in CL Technical Reports
  • "Capability Hardware Enhanced RISC Instructions (CHERI): Notes on the Meltdown and Spectre Attacks" (2021) published in CL Technical Reports

Simon W. Moore frequently collaborates with other researchers. Their most common co-authors include Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, David Chisnall, and Brooks Davis. Collaborations with these researchers span multiple projects and publications.

Their work has been published predominantly in the CL Technical Reports venue, where they have at least eight publications. Other venues include Communications of the ACM, IEEE Micro, IEEE Security & Privacy, and IEEE Design and Test.

Best Publications

  • Low-Latency Virtual-Channel Routers for On-Chip Networks

    Robert Mullins;Andrew West;Simon Moore

  • Efficient physical embedding of topologically complex information processing networks in brains and computer circuits.

    Danielle S. Bassett;Daniel L. Greenfield;Andreas Meyer-Lindenberg;Daniel R. Weinberger

  • CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization

    Robert N.M. Watson;Jonathan Woodruff;Peter G. Neumann;Simon W. Moore

  • The CHERI capability model: revisiting RISC in an age of risk

    Jonathan Woodruff;Robert N.M. Watson;David Chisnall;Simon W. Moore

  • Improving smart card security using self-timed circuits

    S. Moore;R. Anderson;P. Cunningham;R. Mullins

  • A communication characterisation of Splash-2 and Parsec

    Nick Barrow-Williams;Christian Fensch;Simon Moore

  • 2015 IEEE Symposium on Security and Privacy SP 2015

    Jonathan Woodruff;Peter G. Neumann;Simon W. Moore;Jonathan Anderson

  • The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators

    A. Theodore Markettos;Simon W. Moore

  • Point to point GALS interconnect

    S. Moore;G. Taylor;R. Mullins;P. Robinson

  • The design and implementation of a low-latency on-chip network

    Robert Mullins;Andrew West;Simon Moore

  • Workload Characterization, 2009. IISWC 2009. IEEE International Symposium on

    N. Barrow-Williams;Christian Fensch;S. Moore

  • A Power and Energy Exploration of Network-on-Chip Architectures

    A. Banerjee;R. Mullins;S. Moore

  • Bluehive - A field-programable custom computing machine for extreme-scale real-time neural network simulation

    S. W. Moore;P. J. Fox;S. J. T. Marsh;A. T. Markettos

  • Security Evaluation of Asynchronous Circuits

    Jacques J. A. Fournier;Simon W. Moore;Huiyun Li;Robert D. Mullins

  • Balanced self-checking asynchronous logic for smart card applications

    Simon W. Moore;Ross J. Anderson;Robert D. Mullins;George S. Taylor

  • Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine

    David Chisnall;Colin Rothwell;Robert N.M. Watson;Jonathan Woodruff

  • Demystifying Data-Driven and Pausible Clocking Schemes

    R. Mullins;S. Moore

  • Self calibrating clocks for globally asynchronous locally synchronous systems

    S.W. Moore;G.S. Taylor;P.A. Cunningham;R.D. Mullins

  • An Energy and Performance Exploration of Network-on-Chip Architectures

    Amab Banerjee;Pascal T. Wolkotte;Robert D. Mullins;Simon W. Moore

  • A modified multilayer perceptron model for gas mixture analysis

    S.W. Moore;J.W. Gardner;E.L. Hines;W. Göpel

  • Microprocessor resistant to power analysis

    Ross John Anderson;Simon William Moore

Frequent Co-Authors

Peter Sewell
Peter Sewell University of Cambridge
Ross Anderson
Ross Anderson University of Cambridge
Peter Robinson
Peter Robinson University of Cambridge
Gerard J. M. Smit
Gerard J. M. Smit University of Twente
Andreas Meyer-Lindenberg
Andreas Meyer-Lindenberg Heidelberg University
Ian H. White
Ian H. White University of Bath
Richard V. Penty
Richard V. Penty University of Cambridge
Wayne Burleson
Wayne Burleson University of Massachusetts Amherst
Robert A. Holt
Robert A. Holt BC Cancer Research Institute
John L. Williams
John L. Williams University of Adelaide

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