2011 - IEEE Fellow For contributions to power-aware systems and estimation tools
N. Vijaykrishnan focuses on Embedded system, Network on a chip, Energy consumption, Memory architecture and Electronic engineering. His research in Embedded system intersects with topics in Energy conservation, Cache algorithms, Exploit, Interconnection and Error detection and correction. His biological study spans a wide range of topics, including Fault tolerance, System on a chip, Heterogeneous network and Router.
The study incorporates disciplines such as Compiler, Distributed computing, Power budget and Adaptive routing in addition to Energy consumption. His work carried out in the field of Memory architecture brings together such families of science as CPU cache, Cache and Random access memory. Electronic engineering is often connected to Engineering physics in his work.
N. Vijaykrishnan mostly deals with Embedded system, Electronic engineering, Energy consumption, Parallel computing and Cache. His Embedded system research is multidisciplinary, incorporating elements of Compiler and Interconnection. N. Vijaykrishnan focuses mostly in the field of Interconnection, narrowing it down to topics relating to Logic synthesis and, in certain cases, Logic simulation.
His studies in Electronic engineering integrate themes in fields like Low-power electronics and Leakage. His Leakage research includes themes of Electronic circuit, Leakage power and Voltage. His Energy consumption study also includes fields such as
His primary scientific interests are in Electronic engineering, Embedded system, Scalability, Degradation and Reliability. His study looks at the intersection of Electronic engineering and topics like Transistor with Static random-access memory, Leakage and Ultra low power. His study in Embedded system is interdisciplinary in nature, drawing from both Smart Cache, Cache algorithms, Cache coloring, Energy consumption and Interconnection.
His work deals with themes such as Compiler, Error detection and correction, Focus and Very long instruction word, which intersect with Energy consumption. N. Vijaykrishnan combines subjects such as Logic synthesis, Frequency scaling, Throughput, Power management and System on a chip with his study of Interconnection. In his research on the topic of System on a chip, Network planning and design is strongly related with Network on a chip.
His main research concerns Embedded system, Network on a chip, Cache, Interconnection and Router. His Network on a chip research is multidisciplinary, incorporating perspectives in Network planning and design, Mesh networking, Shared resource, Heterogeneous network and Wireless mesh network. His Cache research incorporates elements of Negative-bias temperature instability and Energy conservation.
His Interconnection study combines topics in areas such as Logic synthesis, Computer architecture, System on a chip and Power management. His Router study integrates concerns from other disciplines, such as Frequency scaling, Scalability, Power network design and Throughput. The Cache algorithms study combines topics in areas such as Integrated circuit design and Design space exploration.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Dynamic management of scratch-pad memory space
M. Kandemir;J. Ramanujam;J. Irwin;N. Vijaykrishnan.
design automation conference (2001)
Analysis of error recovery schemes for networks on chips
S. Murali;T. Theocharides;N. Vijaykrishnan;M.J. Irwin.
IEEE Design & Test of Computers (2005)
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Chrysostomos A. Nicopoulos;Dongkook Park;Jongman Kim;N. Vijaykrishnan.
international symposium on microarchitecture (2006)
A low latency router supporting adaptivity for on-chip interconnects
Jongman Kim;Dongkook Park;T. Theocharides;N. Vijaykrishnan.
design automation conference (2005)
Exploring Fault-Tolerant Network-on-Chip Architectures
D. Park;C. Nicopoulos;J. Kim;N. Vijaykrishnan.
dependable systems and networks (2006)
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Dongkook Park;Soumya Eachempati;Reetuparna Das;Asit K. Mishra.
international symposium on computer architecture (2008)
Fault tolerant algorithms for network-on-chip interconnect
M. Pirretti;G.M. Link;R.R. Brooks;N. Vijaykrishnan.
ieee computer society annual symposium on vlsi (2004)
Using complete machine simulation for software power estimation: the SoftWatt approach
S. Gurumurthi;A. Sivasubramaniam;M.J. Irwin;N. Vijaykrishnan.
high-performance computer architecture (2002)
Reducing leakage energy in FPGAs using region-constrained placement
A. Gayasen;Y. Tsai;N. Vijaykrishnan;M. Kandemir.
field programmable gate arrays (2004)
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
W.-L. Hung;G. M. Link;Yuan Xie;N. Vijaykrishnan.
international symposium on quality electronic design (2006)
Profile was last updated on December 6th, 2021.
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