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Vijay Janapa Reddi

Vijay Janapa Reddi

D-Index & Metrics

Computer Science

D-Index
45
Citations
13900
World Ranking
7029
National Ranking
3082

Overview

Vijay Janapa Reddi is affiliated with Harvard University in the United States and has made contributions primarily in the fields of Computer Science and Engineering. Their work is distributed across multiple subfields including Artificial Intelligence, Electrical and Electronic Engineering, Computer Vision and Pattern Recognition, Computer Networks and Communications, and Hardware and Architecture.

Their research addresses a range of main topics such as Advanced Memory and Neural Computing, Advanced Neural Network Applications, Robotics and Sensor-Based Localization, Parallel Computing and Optimization Techniques, Robotic Path Planning Algorithms, Adversarial Robustness in Machine Learning, and IoT and Edge/Fog Computing.

Vijay Janapa Reddi has collaborated frequently with a group of coauthors, including Srivatsan Krishnan, Brian Plancher, Zishen Wan, Colby Banbury, and Aleksandra Faust.

The scientist's publication record features significant contributions to various venues. The most frequent publication outlets include:

  • arXiv (Cornell University)
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Zenodo (CERN European Organization for Nuclear Research)
  • IEEE Micro
  • Communications of the ACM

Among the recent papers attributed to Vijay Janapa Reddi are:

  • Deep Reinforcement Learning for Cyber Security, 2021, IEEE Transactions on Neural Networks and Learning Systems
  • Benchmarking TinyML Systems: Challenges and Direction, 2020, arXiv (Cornell University)
  • TensorFlow Lite Micro: Embedded Machine Learning on TinyML Systems, 2020, arXiv (Cornell University)
  • MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance, 2020, IEEE Micro
  • MicroNets: Neural Network Architectures for Deploying TinyML Applications on Commodity Microcontrollers, 2020, arXiv (Cornell University)

Best Publications

  • Pin: building customized program analysis tools with dynamic instrumentation

    Chi-Keung Luk;Robert Cohn;Robert Muth;Harish Patil

  • GPUWattch: enabling energy optimizations in GPGPUs

    Jingwen Leng;Tayler Hetherington;Ahmed ElTantawy;Syed Gilani

  • Deep Reinforcement Learning for Cyber Security.

    Thanh Thi Nguyen;Vijay Janapa Reddi

  • MLPerf inference benchmark

    Vijay Janapa Reddi;Christine Cheng;David Kanter;Peter Mattson

  • A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance

    Qiang Wu;Margaret Martonosi;Douglas W. Clark;V. J. Reddi

  • Web search using mobile cores: quantifying and mitigating the price of efficiency

    Vijay Janapa Reddi;Benjamin C. Lee;Trishul Chilimbi;Kushagra Vaid

  • PIN: a binary instrumentation tool for computer architecture research and education

    Vijay Janapa Reddi;Alex Settle;Daniel A. Connors;Robert S. Cohn

  • Benchmarking TinyML Systems: Challenges and Direction

    Colby R. Banbury;Vijay Janapa Reddi;Max Lam;William Fu

  • PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures

    A. Shye;J. Blomstedt;T. Moseley;V.J. Reddi

  • High-performance and energy-efficient mobile web browsing on big/little systems

    Yuhao Zhu;V. J. Reddi

  • MLPerf Training Benchmark.

    Peter Mattson;Christine Cheng;Cody Coleman;Greg Diamos

  • Mobile CPU's rise to power: Quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction

    Matthew Halpern;Yuhao Zhu;Vijay Janapa Reddi

  • TensorFlow Lite Micro: Embedded Machine Learning on TinyML Systems

    Robert David;Jared Duke;Advait Jain;Vijay Janapa Reddi

  • Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance

    A. Shye;T. Moseley;V.J. Reddi;J. Blomstedt

  • MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance

    Peter Mattson;Hanlin Tang;Gu-Yeon Wei;Carole-Jean Wu

  • Voltage emergency prediction: Using signatures to reduce operating margins

    Vijay Janapa Reddi;Meeta S. Gupta;Glenn Holloway;Gu-Yeon Wei

  • MicroNets: Neural Network Architectures for Deploying TinyML Applications on Commodity Microcontrollers

    Colby R. Banbury;Chuteng Zhou;Igor Fedorov;Ramon Matas Navarro

  • Event-based scheduling for energy-efficient QoS (eQoS) in mobile Web applications

    Yuhao Zhu;Matthew Halpern;Vijay Janapa Reddi

  • Shadow Profiling: Hiding Instrumentation Costs with Parallelism

    Tipp Moseley;Alex Shye;Vijay Janapa Reddi;Dirk Grunwald

  • Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

    Vijay Janapa Reddi;Svilen Kanev;Wonyoung Kim;Simone Campanoni

  • MLPerf Training Benchmark

    Peter Mattson;Christine Cheng;Gregory F. Diamos;Cody Coleman

  • HELIX: automatic parallelization of irregular programs for chip multiprocessing

    Simone Campanoni;Timothy Jones;Glenn Holloway;Vijay Janapa Reddi

  • Proceedings of the 2017 International Symposium on Code Generation and Optimization

    Vijay Janapa Reddi;Aaron Smith;Lingjia Tang

Frequent Co-Authors

David Brooks
David Brooks Harvard University
Gu-Yeon Wei
Gu-Yeon Wei Harvard University
Gennady Pekhimenko
Gennady Pekhimenko University of Toronto
Carole-Jean Wu
Carole-Jean Wu Meta Platforms, Inc.
Alper Buyuktosunoglu
Alper Buyuktosunoglu IBM (United States)
Pradip Bose
Pradip Bose IBM (United States)
Peter Bailis
Peter Bailis Stanford University
David A. Patterson
David A. Patterson University of California, Berkeley
Kim Hazelwood
Kim Hazelwood Facebook (United States)
Arijit Raychowdhury
Arijit Raychowdhury Georgia Institute of Technology

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