T. Poiroux

Best Publications

• Advances, challenges and opportunities in 3D CMOS sequential integration

  P. Batude;M. Vinet;B. Previtali;C. Tabone

  325
  Citations

• Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

  S. Barraud;M. Berthome;R. Coquand;M. Casse

  269
  Citations

• Multi- $V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

  J-P Noel;O. Thomas;M. Jaud;O. Weber

  255
  Citations

• Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

  O. Faynot;F. Andrieu;O. Weber;C. Fenouillet-Beranger

  237
  Citations

• Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length

  P. Batude;M. Vinet;C. Xu;B. Previtali

  184
  Citations

• Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

  E. Bernard;T. Ernst;B. Guillaumot;N. Vulliet

  176
  Citations

• Multiple gate devices: advantages and challenges

  T. Poiroux;M. Vinet;O. Faynot;J. Widiez

  170
  Citations

• Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

  S. Barraud;R. Coquand;M. Casse;M. Koyama

  166
  Citations

• Bonded planar double-metal-gate NMOS transistors down to 10 nm

  M. Vinet;T. Poiroux;J. Widiez;J. Lolivier

  153
  Citations

• Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

  F. Andrieu;O. Weber;J. Mazurier;O. Thomas

  111
  Citations

• 14nm FDSOI technology for high speed and energy efficient applications

  Olivier Weber;E. Josse;F. Andrieu;A. Cros

  111
  Citations

• New Mechanism of Body Charging in Partially Depleted SOI-MOSFETs with Ultra-thin Gate Oxides

  J. Pretet;T. Matsumoto;T. Poiroux;S. Cristoloveanu

  99
  Citations

• Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance

  Unknown

  96
  Citations

• Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO 2 gate stack

  V. Barral;T. Poiroux;F. Andrieu;C. Buj-Dufournet

  92
  Citations

• Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

  R. Coquand;M. Casse;S. Barraud;D. Cooper

  89
  Citations

• Strained tunnel FETs with record I ON : first demonstration of ETSOI TFETs with SiGe channel and RSD

  A. Villalon;C. Le Royer;M. Casse;D. Cooper

  85
  Citations

• Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

  R. Coquand;S. Barraud;M. Casse;P. Leroux

  74
  Citations

• Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width

  R. Coquand;R. Coquand;S. Barraud;M. Casse;P. Leroux

  69
  Citations

• Size Dependence of Surface-Roughness-Limited Mobility in Silicon-Nanowire FETs

  Unknown

  69
  Citations

• Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part I: Interface Potentials Analytical Model

  Unknown

  68
  Citations