S. Biesemans

Best Publications

• Gate-induced quantum-confinement transition of a single dopant atom in a silicon FinFET

  G P Lansbergen;R Rahman;C J Wellard;I Woo

  434
  Citations

• Transport spectroscopy of a single dopant in a gated silicon nanowire.

  H. Sellier;G. P. Lansbergen;J. Caro;S. Rogge

  344
  Citations

• Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

  L.-A. Ragnarsson;Z. Li;J. Tseng;T. Schram

  226
  Citations

• Modulation of the Ni FUSI workfunction by Yb doping: from midgap to n-type band-edge

  H.Y. Yu;J.D. Chen;M.F. Li;S.J. Lee

  207
  Citations

• Review of FINFET technology

  M. Jurczak;N. Collaert;A. Veloso;T. Hoffmann

  191
  Citations

• 3D stacked IC demonstration using a through Silicon Via First approach

  J. Van Olmen;A. Mercha;G. Katti;C. Huyghebaert

  186
  Citations

• Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

  T. Chiarella;L. Witters;A. Mercha;C. Kerner

  155
  Citations

• Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

  A. Mercha;G. Van der Plas;V. Moroz;I. De Wolf

  142
  Citations

• Multi-gate devices for the 32 nm technology node and beyond

  N. Collaert;A. De Keersgieter;A. Dixit;I. Ferain

  137
  Citations

• Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

  M. J. H. van Dal;N. Collaert;G. Doornbos;G. Vellianitis

  116
  Citations

• Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

  S. B. Samavedam;J. Ryckaert;E. Beyne;K. Ronse

  103
  Citations

• Tall triple-gate devices with TiN/HfO/sub 2/ gate stack

  N. Collaert;M. Demand;I. Ferain;J. Lisoni

  100
  Citations

• A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node

  N. Collaert;A. Dixit;M. Goodwin;K.G. Anil

  97
  Citations

• Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

  J.A. Kittl;M.A. Pawlak;A. Lauwers;C. Demeurisse

  88
  Citations

• Multi-gate devices for the 32nm technology node and beyond

  N. Collaert;A. De Keersgieter;A. Dixit;I. Ferain

  87
  Citations

• Layout impact on the performance of a locally strained PMOSFET

  G. Eneman;P. Verheyen;R. Rooyackers;F. Nouri

  85
  Citations

• 3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding

  G. Katti;A. Mercha;J. Van Olmen;C. Huyghebaert

  85
  Citations

• Composition influence on the physical and electrical properties of SrxTi1-xOy-based metal-insulator-metal capacitors prepared by atomic layer deposition using TiN bottom electrodes

  N. Menou;M. Popovici;S. Clima;K. Opsomer

  83
  Citations

• Wide $V_{ m fb}$ and $V_{ m th}$ Tunability for Metal-Gated MOS Devices With HfLaO Gate Dielectrics

  X.P. Wang;H.Y. Yu;M.-F. Li;M.-F. Li;C.X. Zhu

  70
  Citations

• Performance Enhancement of MUGFET Devices Using Super Critical Strained-SOI (SC-SSOI) and CESL

  N. Collaert;R. Rooyackers;F. Clemente;P. Zimmerman

  70
  Citations