2026 Rajit Manohar: Engineering and Technology Researcher – H-Index, Publications & Awards

D-Index & Metrics

Discipline name	D-Index	World Ranking	Current World Ranking	National Ranking	Current National Ranking	Publications	Citations
Engineering and Technology	33	9310	8958	2604	2403	163	11375

Discipline name

D-Index

World Ranking

Current World Ranking

National Ranking

Current National Ranking

Publications

Citations

Engineering and Technology

9310

8958

2604

2403

163

11375

Engineering and Technology

D-Index

Citations

11375

World Ranking

9310

National Ranking

2604

Overview

Rajit Manohar is affiliated with Yale University in the United States and has an extensive body of research spanning engineering, computer science, and neuroscience. Their work primarily focuses on the intersections of advanced memory and neural computing, low-power high-performance VLSI design, and neuroscience and neural engineering.

The main fields of study for Rajit Manohar include:

Engineering
Computer Science
Neuroscience

Within these areas, the subfields of study often addressed are:

Electrical and Electronic Engineering
Hardware and Architecture
Cognitive Neuroscience
Cellular and Molecular Neuroscience
Artificial Intelligence

The main topics covered by Rajit Manohar's research work encompass:

Advanced Memory and Neural Computing
Low-power high-performance VLSI design
Neuroscience and Neural Engineering
VLSI and FPGA Design Techniques
EEG and Brain-Computer Interfaces
Ferroelectric and Negative Capacitance Devices
VLSI and Analog Circuit Testing

Rajit Manohar has co-authored publications with several frequent collaborators, including:

Karthik Sriram
Abhishek Bhattacharjee
Jiayuan He
Keshav Pingali
Raghavendra Pradyumna Pothukuchi

The scientist's published papers appear notably in venues such as:

arXiv (Cornell University)
IEEE Micro
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JMIR Formative Research
Nature Communications

Selected recent papers by Rajit Manohar include:

The neurobench framework for benchmarking neuromorphic computing algorithms and systems, 2025, Nature Communications
SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity, 2022, 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)
An Open-Source EDA Flow for Asynchronous Logic, 2021, IEEE Design and Test
NeuroBench: A Framework for Benchmarking Neuromorphic Computing Algorithms and Systems, 2023, Lirias (KU Leuven)
Pilot Evaluations of Two Bluetooth Contact Tracing Approaches on a University Campus: Mixed Methods Study, 2021, JMIR Formative Research

Best Publications

A million spiking-neuron integrated circuit with a scalable communication network and interface

Paul A. Merolla;John V. Arthur;Rodrigo Alvarez-Icaza;Andrew S. Cassidy

4322
Citations
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

Filipp Akopyan;Jun Sawada;Andrew Cassidy;Rodrigo Alvarez-Icaza

1659
Citations
A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm

Paul Merolla;John Arthur;Filipp Akopyan;Nabil Imam

575
Citations
The design of an asynchronous MIPS R3000 microprocessor

A.J. Martin;A. Lines;R. Manohar;M. Nystrom

440
Citations
Highly pipelined asynchronous FPGAs

John Teifel;Rajit Manohar

239
Citations
Braindrop: A Mixed-Signal Neuromorphic Architecture With a Dynamical Systems-Based Programming Model

Alexander Neckar;Sam Fok;Ben V. Benjamin;Terrence C. Stewart

223
Citations
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core

John V. Arthur;Paul A. Merolla;Filipp Akopyan;Rodrigo Alvarez

197
Citations
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor

C. LaFrieda;E. Ipek;J.F. Martinez;R. Manohar

186
Citations
An asynchronous dataflow FPGA architecture

J. Teifel;R. Manohar

183
Citations
An ultra low-power processor for sensor networks

Virantha Ekanayake;Clinton Kelly;Rajit Manohar

162
Citations
Programmable asynchronous pipeline arrays

John R. Teifel;Rajit Manohar

156
Citations
A level-crossing flash asynchronous analog-to-digital converter

F. Akopyan;R. Manohar;A.B. Apsel

139
Citations
Asynchronous analog-to-digital converter and method

Filipp Akopyan;Alyssa Apsel;Rajit Manohar

126
Citations
Neuromorphic event-driven neural computing architecture in a scalable neural network

Filipp Akopyan;John V. Arthur;Rajit Manohar;Paul A. Merolla

124
Citations
Slack Elasticity in Concurrent Computing

Rajit Manohar;Alain J. Martin

116
Citations
Real-time scalable cortical computing at 46 giga-synaptic OPS/watt with ~100× speedup in time-to-solution and ~100,000× reduction in energy-to-solution

Andrew S. Cassidy;Rodrigo Alvarez-Icaza;Filipp Akopyan;Jun Sawada

99
Citations
Pipelined asynchronous processing

Alain J. Martin;Andrew Lines;Rajit Manohar;Uri Cummings

88
Citations
Fault detection and isolation techniques for quasi delay-insensitive circuits

C. LaFrieda;R. Manohar

88
Citations
SNAP: a Sensor-Network Asynchronous Processor

C. Kelly;V. Ekanayake;R. Manohar

86
Citations
Automated conversion of synchronous to asynchronous circuit design representations

Rajit Manohar

83
Citations