His primary areas of study are Optoelectronics, Electronic engineering, Layer, Gate oxide and MOSFET. He has included themes like Metal gate, Polysilicon depletion effect, Transistor, Substrate and Electrical engineering in his Optoelectronics study. His work carried out in the field of Transistor brings together such families of science as Nanotechnology, Silicon-germanium, Quantum tunnelling, CMOS and Band gap.
His Electronic engineering research integrates issues from Silicon, Copper interconnect, Sheet resistance, Salicide and Insulator. Lap Chan has researched Layer in several fields, including Electrode, Dielectric and Voltage. The MOSFET study combines topics in areas such as Silicon on insulator, Atomic physics and First principle.
His primary areas of investigation include Optoelectronics, Layer, Electronic engineering, Silicon and Analytical chemistry. His Optoelectronics study combines topics in areas such as Transistor, Substrate, Gate oxide, MOSFET and Electrical engineering. Lap Chan has researched Layer in several fields, including Oxide and Electrode.
His Electronic engineering research incorporates themes from Sheet resistance, Photoresist, Semiconductor and Integrated circuit. As part of one scientific family, Lap Chan deals mainly with the area of Silicon, narrowing it down to issues related to the Ion implantation, and often Dopant. His research in Analytical chemistry intersects with topics in Wafer, Annealing and Copper.
Optoelectronics, Transistor, MOSFET, Silicon and Impact ionization are his primary areas of study. Lap Chan studies CMOS, a branch of Optoelectronics. His work carried out in the field of Transistor brings together such families of science as Band gap and Silicon-germanium.
His studies in MOSFET integrate themes in fields like Silicon on insulator, Stress, Composite material and Gate oxide. His Silicon research is multidisciplinary, incorporating perspectives in Ion implantation, Dopant Activation, Dopant and Annealing. Lap Chan combines subjects such as Epitaxy and Strain engineering with his study of Impact ionization.
Lap Chan mostly deals with Optoelectronics, Transistor, Silicon, Nanotechnology and Field-effect transistor. Lap Chan has included themes like Breakdown voltage, MOSFET, Threshold voltage, Static induction transistor and Strain engineering in his Optoelectronics study. His MOSFET study is concerned with the field of Electrical engineering as a whole.
His Transistor research incorporates elements of Ultimate tensile strength, Impact ionization, Silicon-germanium, CMOS and Band gap. His CMOS research is multidisciplinary, incorporating elements of Substrate and Semiconductor device. His work deals with themes such as Condensed matter physics, Doping, Annealing, Ion implantation and Schottky barrier, which intersect with Silicon.
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Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer
Cher Liang Cha;Alex See;Lap Chan.
Method for planarized interconnect vias using electroless plating and CMP
Chan Lap;Tee Ng Hou.
Creation of a self-aligned, ion implanted channel region, after source and drain formation
Teck Koon Lee;Lap Chan;Chock H. Gan;Po-Ching Liu.
Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance
Wong Harianto;Pey Kin Leong;Chen Lap.
Method for shallow trench isolation
Jia Zhen Zheng;Charlie Wee Song Tay;Wei Lu;Lap Chan.
Passivation of copper interconnect surfaces with a passivating metal layer
Lap Chan;Kuan Pei Yap;Kheng Chok Tee;Flora S. Ip.
Method to form a self-aligned CMOS inverter using vertical device integration
Ravi Sundaresan;Yang Pan;James Yong Meng Lee;Ying Keung Leung.
New salicidation technology with Ni(Pt) alloy for MOSFETs
P.S. Lee;K.L. Pey;D. Mangelinck;J. Ding.
IEEE Electron Device Letters (2001)
Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction
Eng-Huat Toh;Grace Huiqi Wang;Lap Chan;Ganesh Samudra.
Applied Physics Letters (2007)
A method to form a transistor with multiple threshold voltages using a combination of different work function gate materials
Lap Chan;Elgin Quek;Ravi Sundaresan;Yang Pan.
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