World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
43
Citations
7588
World Ranking
3896
National Ranking
1403

Research.com Recognitions

  • 2011 - IEEE Fellow For contributions to high-performance mixed-signal integrated circuits using digital calibration techniques

Overview

Ian Galton is affiliated with the University of California, San Diego in the United States. Their research spans fields including Engineering and Neuroscience, with particular focus on Electrical and Electronic Engineering, Cognitive Neuroscience, Cellular and Molecular Neuroscience, Biomedical Engineering, and Biophysics.

The scientist's work addresses several main topics:

  • EEG and Brain-Computer Interfaces
  • Neuroscience and Neural Engineering
  • Advancements in PLL and VCO Technologies
  • Radio Frequency Integrated Circuit Design
  • Analog and Mixed-Signal Circuit Design
  • Advanced Memory and Neural Computing
  • Neural dynamics and brain function

Ian Galton's publication record includes articles in multiple venues. Frequent publication outlets are:

  • IEEE Transactions on Circuits and Systems I Regular Papers
  • IEEE Journal of Solid-State Circuits
  • Science Translational Medicine
  • arXiv (Cornell University)
  • Neuromodulation Technology at the Neural Interface

Notable recent papers authored by or coauthored with Ian Galton include:

  • "Human brain mapping with multithousand-channel PtNRGrids resolves spatiotemporal dynamics" (2022, Science Translational Medicine)
  • "An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs" (2021, IEEE Journal of Solid-State Circuits)
  • "A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL" (2021, IEEE Journal of Solid-State Circuits)
  • "Intraoperative application and early experience with novel high-resolution, high-channel-count thin-film electrodes for human microelectrocorticography" (2023, Journal of neurosurgery)
  • "An electroencephalogram microdisplay to visualize neuronal activity on the brain surface" (2024, Science Translational Medicine)

Frequent collaborators who have coauthored multiple papers with Ian Galton include:

  • Shadi A. Dayeh
  • Youngbin Tchoe
  • Karen J. Tonsfeldt
  • Angelique C. Paulk
  • Jimmy C. Yang

Ian Galton has been recognized as an IEEE Fellow since 2011 for contributions to high-performance mixed-signal integrated circuits using digital calibration techniques.

Best Publications

  • Spectral shaping of circuit errors in digital-to-analog converters

    I. Galton

  • A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation

    S. Pamarti;L. Jansson;I. Galton

  • A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

    Eric Siragusa;Ian Galton

  • A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC

    G Taylor;I Galton

  • A multiple-crystal interface PLL with VCO realignment to reduce phase noise

    Sheng Ye;L. Jansson;I. Galton

  • A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction

    Andrea Panigada;Ian Galton

  • Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional- N PLL

    K.J. Wang;A. Swaminathan;I. Galton

  • Digital cancellation of D/A converter noise in pipelined A/D converters

    I. Galton

  • Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL

    K.J. Wang;A. Swaminathan;I. Galton

  • A Wide-Bandwidth 2.4 GHz ISM Band Fractional- $N$ PLL With Adaptive Phase Noise Cancellation

    A. Swaminathan;K.J. Wang;I. Galton

  • Delta-sigma data conversion in wireless transceivers

    I. Galton

  • Delta-Sigma modulator based A/D conversion without oversampling

    I. Galton;H.T. Jensen

  • Synergistic design of DSP and power amplifiers for wireless communications

    P.M. Asbeck;L.E. Larson;I.G. Galton

  • Combined angle demodulator and digitizer

    Ian Galton

  • A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB

    G. Taylor;I. Galton

  • Digital Background Correction of Harmonic Distortion in Pipelined ADCs

    A. Panigada;I. Galton

  • Digital generation of RF signals for wireless communications with band-pass delta-sigma modulation

    J. Keyzer;J. Hinrichs;A. Metzger;M. Iwamoto

  • Why Dynamic-Element-Matching DACs Work

    I. Galton

  • A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction

    Unknown

  • A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB

    Gerry Taylor;Ian Galton

  • Radio transmission frequency digital signal generation

    Peter M. Asbeck;Ian Galton

  • Gain error correction technique for pipelined analogue-to-digital converters

    E.J. Siragusa;I. Galton

Frequent Co-Authors

Peter M. Asbeck
Peter M. Asbeck University of California, San Diego
Lawrence E. Larson
Lawrence E. Larson Brown University
Terri S. Fiez
Terri S. Fiez University of Colorado Boulder
Gabor C. Temes
Gabor C. Temes Oregon State University
Behzad Razavi
Behzad Razavi University of California, Los Angeles
Bram Nauta
Bram Nauta University of Twente
Robert Bogdan Staszewski
Robert Bogdan Staszewski University College Dublin
Peter R. Kinget
Peter R. Kinget Columbia University
Seth R. Sanders
Seth R. Sanders University of California, Berkeley
Sang-Gug Lee
Sang-Gug Lee Korea Advanced Institute of Science and Technology

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