D. Schmitt-Landsiedel

Overview

Best Publications

• Yield and speed optimization of a latch-type voltage sense amplifier

  Unknown

  567
  Citations

• Complementary tunneling transistor for low power application

  Unknown

  562
  Citations

• A 128 × 128 CMOS bio-sensor array for extracellular recording of neural activity

  B. Eversmann;M. Jenkner;C. Paulus;F. Hofmann

  450
  Citations

• A 0.5-V 1-μW successive approximation ADC

  Unknown

  268
  Citations

• Invasive Computing: An Overview

  Jürgen Teich;Jörg Henkel;Andreas Herkersdorf;Doris Schmitt-Landsiedel

  182
  Citations

• Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

  Marcus Weis;Andrzej Pfitzner;Dominik Kasprowicz;Rainer Emling

  175
  Citations

• Scaling properties of the tunneling field effect transistor (TFET): Device and circuit

  Unknown

  115
  Citations

• A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology

  Unknown

  108
  Citations

• Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation

  B. Hoppe;G. Neuendorf;D. Schmitt-Landsiedel;W. Specks

  102
  Citations

• Yield-oriented computer-aided defect diagnosis

  J.B. Khare;W. Maly;S. Griep;D. Schmitt-Landsiedel

  92
  Citations

• The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes

  Unknown

  90
  Citations

• A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS

  Unknown

  79
  Citations

• Dynamic degradation in MOSFET's. II. Application in the circuit environment

  Unknown

  78
  Citations

• Experimental Demonstration of a 1-Bit Full Adder in Perpendicular Nanomagnetic Logic

  Unknown

  75
  Citations

• A Pipelined 330 MHz Multiplier

  Unknown

  71
  Citations

• In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations

  Unknown

  60
  Citations

• Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS

  Unknown

  60
  Citations

• Pipelined architecture for fast CMOS buffer RAMs

  D. Schmitt-Landsiedel;B. Hoppe;G. Neuendorf;M. Wurm

  58
  Citations

• Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems

  Unknown

  54
  Citations

• RF ESD protection strategies: Codesign vs. low-C protection

  W. Soldner;M. Streibl;U. Hodel;M. Tiebout

  53
  Citations

• 1-Bit Full Adder in Perpendicular Nanomagnetic Logic using a Novel 5-Input Majority Gate

  Stephan Breitkreutz;Irina Eichwald;Josef Kiermaier;Adam Papp

  30
  Citations

• Field-coupled nanomagnets for interconnect-free nonvolatile computing

  M. Becherer;G. Csaba;R. Emling;W. Porod

  30
  Citations

• Field-coupled computing in magnetic multilayers

  György Csaba;Paolo Lugli;Markus Becherer;Doris Schmitt-Landsiedel

  25
  Citations

• On-chip Extraordinary Hall-effect sensors for characterization of nanomagnetic logic devices

  M. Becherer;J. Kiermaier;S. Breitkreutz;G. Csaba

  24
  Citations

• SRAM-based extraction of defect characteristics

  J. Khare;W. Maly;S. Griep;D. Schmitt-Landsiedel

  24
  Citations

• Four-phase power clock generator for adiabatic logic circuits

  A. Bargagli-Stoffi;G. Iannaccone;S. Di Pascoli;E. Amirante

  21
  Citations

• Clocking Schemes for Field Coupled Devices from Magnetic Multilayers

  Nikolaos Rizos;Murad Omar;Paolo Lugli;Gyorgy Csaba

  19
  Citations

• AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout

  I. Bubel;W. Maly;T. Waas;P.K. Nag

  18
  Citations

• Misuse protection device for chip card security system

  Max Dipl Ing Steger;Christopher Dr Hierold;Roland Dipl Ing Thewes;Manfred Dipl Ing Mauthe

  16
  Citations

• Layout options for stability tuning of SRAM cells in multi-gate-FET technologies

  F. Bauer;K. von Arnim;C. Pacha;T. Schulz

  14
  Citations

• Adder circuits with transistors using independently controlled gates

  Marcus Weis;Andrzej Pfitzner;Dominik Kasprowicz;Rainer Emling

  13
  Citations

• Clocking magnetic field-coupled devices by domain walls

  György Csaba;Josef Kiermaier;Markus Becherer;Stephan Breitkreutz

  12
  Citations

• Design of low-voltage MOSFET-only ΣΔ modulators in standard digital CMOS technology.

  Thomas Tille;Jens Sauerbrey;Manfred Mauthe;Doris Schmitt-Landsiedel

  9
  Citations

• Low Power VCO Design in CMOS

  Kiyoo Itoh;Thomas Lee;Takayasu Sakurai;Willy M. C. Sansen

  9
  Citations

• Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing

  Jürgen Fischer;Ettore Amirante;Francesco Randazzo;Giuseppe Iannaccone

  6
  Citations