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D-Index & Metrics

Computer Science

D-Index
32
Citations
4143
World Ranking
13205
National Ranking
5298

Overview

Pranav Ashar is affiliated with NEC in the United States. The available data does not list specific research papers, co-authors, or publication venues associated with their work.

Details regarding Ashar's main fields of study, subfields, and main topics of work are not provided. Similarly, information about any book publications or awards is not presented.

This profile is based on currently accessible data about Pranav Ashar's professional and academic background, which primarily identifies their institutional affiliation without further specifics on research contributions or scholarly output.

Best Publications

  • Guarded evaluation: pushing power management to logic synthesis/design

    V. Tiwari;S. Malik;P. Ashar

  • Technology mapping for lower power

    Vivek Tiwari;Pranav Ashar;Sharad Malik

  • Simulation vector generation from HDL descriptions for observability-enhanced statement coverage

    Farzan Fallah;Pranav Ashar;Srinivas Devadas

  • Technology Mapping for Low Power

    V. Tiwari;P. Ashar;S. Malik

  • Verification of scheduling in the presence of loops using uninterpreted symbolic simulation

    P. Ashar;A. Raghunathan;A. Gupta;S. Bhattacharya

  • Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver

    M.K. Ganai;Lintao Zhang;P. Ashar;A. Gupta

  • Scheduling techniques to enable power management

    José Monteiro;Srinivas Devadas;Pranav Ashar;Ashutosh Mauskar

  • F-SOFT: software verification platform

    F. Ivančić;Z. Yang;M. K. Ganai;A. Gupta

  • Efficient SAT-based bounded model checking for software verification

    Franjo Ivančić;Zijiang Yang;Malay K. Ganai;Aarti Gupta

  • SAT-Based Image Computation with Application in Reachability Analysis

    Aarti Gupta;Zijiang Yang;Pranav Ashar;Anubhav Gupta

  • Sequential Logic Synthesis

    Pranav Ashar;Srinivas Devadas;A. Richard Newton

  • Fast functional simulation using branching programs

    Pranav Ashar;Sharad Malik

  • Iterative Abstraction using SAT-based BMC with Proof Analysis

    Aarti Gupta;Malay Ganai;Zijiang Yang;Pranav Ashar

  • Accelerating Boolean satisfiability with configurable hardware

    Peixin Zhong;M. Martonosi;P. Ashar;S. Malik

  • Guarded evaluation: pushing power management to logic synthesis/design

    Vivek Tiwari;Sharad Malik;Pranav Ashar

  • Partition-based decision heuristics for image computation using SAT and BDDs

    Aarti Gupta;Zijiang Yang;Pranav Ashar;Lintao Zhang

  • Efficient SAT-based unbounded symbolic model checking using circuit cofactoring

    M. K. Ganai;A. Gupta;P. Ashar

  • Content-based information retrieval architecture

    Shihari Cadambi;Joseph Kilian;Pranav N. Ashar;Srimat T. Chakradhar

  • Using reconfigurable computing techniques to accelerate problems in the CAD domain: a case study with Boolean satisfiability

    Peixin Zhong;Pranav Ashar;Sharad Malik;Margaret Martonosi

  • Toward formalizing a validation methodology using simulation coverage

    Aarti Gupta;Sharad Malik;Pranav Ashar

  • Using configurable computing to accelerate Boolean satisfiability

    Peixin Zhong;M. Martonosi;M. Martonosi;P. Ashar;S. Malik

  • Optimum and heuristic algorithms for an approach to finite state machine decomposition

    P. Ashar;S. Devadas;A.R. Newton

  • Learning from BDDs in SAT-based bounded model checking

    Aarti Gupta;Malay Ganai;Chao Wang;Zijiang Yang

Frequent Co-Authors

Sharad Malik
Sharad Malik Princeton University
Aarti Gupta
Aarti Gupta Princeton University
Margaret Martonosi
Margaret Martonosi Princeton University
A.R. Newton
A.R. Newton University of California, Berkeley
Zijiang Yang
Zijiang Yang Western Michigan University
Franjo Ivancic
Franjo Ivancic Google (United States)
Srimat T. Chakradhar
Srimat T. Chakradhar NEC (United States)
Anand Raghunathan
Anand Raghunathan Purdue University West Lafayette
Sujit Dey
Sujit Dey University of California, San Diego

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