World's Best Scientists 2026 revealed!

D-Index & Metrics

Materials Science

D-Index
58
Citations
14194
World Ranking
7608
National Ranking
1892

Best Publications

  • Sub-10 nm carbon nanotube transistor.

    Aaron D. Franklin;Mathieu Luisier;Shu-Jen Han;George Tulevski

  • Stable SRAM cell design for the 32 nm node and beyond

    L. Chang;D.M. Fried;J. Hergenrother;J.W. Sleight

  • High-performance CMOS variability in the 65-nm regime and beyond

    K. Bernstein;D. J. Frank;A. E. Gattiker;W. Haensch

  • Silicon CMOS devices beyond scaling

    W. Haensch;E. J. Nowak;R. H. Dennard;P. M. Solomon

  • Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics

    Qing Cao;Shu Jen Han;George S. Tulevski;Yu Zhu

  • High-density integration of carbon nanotubes via chemical self-assembly

    Hongsik Park;Ali Afzali;Shu-Jen Han;George S. Tulevski

  • Interconnects in the third dimension: design challenges for 3D ICs

    Kerry Bernstein;Paul Andry;Jerome Cann;Phil Emma

  • Toward High-Performance Digital Logic Technology With Carbon Nanotubes

    George S. Tulevski;Aaron D. Franklin;David Frank;Jose M. Lobez

  • Ultralow-voltage, minimum-energy CMOS

    S. Hanson;B. Zhai;K. Bernstein;D. Blaauw

  • Graphene radio frequency receiver integrated circuit

    Shu-Jen Han;Alberto Valdes Garcia;Satoshi Oida;Keith A. Jenkins

  • The effective drive current in CMOS inverters

    M.H. Na;E.J. Nowak;W. Haensch;J. Cai

  • Extreme scaling with ultra-thin Si channel MOSFETs

    B. Doris;Meikei Ieong;T. Kanarsky;Ying Zhang

  • Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation

    J. Kedzierski;E. Nowak;T. Kanarsky;Y. Zhang

  • End-bonded contacts for carbon nanotube transistors with low, size-independent resistance.

    Qing Cao;Shu-Jen Han;Jerry Tersoff;Aaron D. Franklin

  • A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements

    C.-S. Lee;E. Pop;A. D. Franklin;W. Haensch

  • Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

    K.W. Guarini;A.W. Topol;M. Ieong;R. Yu

  • Practical Strategies for Power-Efficient Computing Technologies

    L. Chang;D.J. Frank;R.K. Montoye;S.J. Koester

  • High frequency graphene Voltage amplifier

    Shu Jen Han;Keith A. Jenkins;Alberto Valdes Garcia;Aaron D. Franklin

  • Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources

    Zhen Zhang;F Pagette;C D'Emic;B Yang

  • The Next Generation of Deep Learning Hardware: Analog Computing

    Wilfried Haensch;Tayfun Gokmen;Ruchir Puri

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