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IEEE

International Symposium on Quality Electronic Design (ISQED)

Location: San Francisco , United States

Conference dates: 4/5/2023 - 4/8/2023

Research H-index
9

Ranking & Metrics

Discipline name Position Best Scientists Publications D-Index
Electronics and Electrical Engineering 188 67 98 8
Engineering and Technology 131 8 15 5

Call for Papers

The details of various topics of paper submission are as follows:

Hardware and System Security (HSS)
Attacks and countermeasures including but not limited to side-channel attacks, reverse engineering, tampering, and Trojans
Hardware-based security primitives including PUFs, TRNGs and ciphers
Security, privacy, trust protocols, and trusted information flow
Ensuring trust using untrusted tools, IP, models and manufacturing
Secure hardware architectures Secure memory systems
Post-quantum security primitives
Security challenges and opportunities of emerging nanoscale devices
IoT and cyber-physical system security
Any other topics related to hardware security
Electronic Design Automation Tools and Methodologies (EDA)
EDA and physical design tools, processes, methodologies, and flows
Design tools for analysis/ tolerance of variation, aging, and soft-errors
Design and maintenance of hard and soft IP blocks
Challenges and solutions of integrating, testing, qualifying and manufacturing IP blocks from multiple vendors
EDA for non-traditional problems such as smart power grid and solar energy
EDA tools and methodologies for 3D integrations, and advanced packaging
Modeling and Simulation of Semiconductor Processes and Devices (TCAD)
CAD for bio-inspired and neuromorphic systems
EDA tools, methodologies and applications for Photonics devices, circuit and system design
EDA for MEMS Any other topics related design automation tools and methodologies
Design Test and Verification (DTV)
Hardware and software formal-, assertion-, and simulation-based design verification techniques
All areas of DFT, ATE and BIST for digital designs, analog/mixed-signal IC's, SoC's, and memories
Test synthesis and synthesis for testability
Fault diagnosis, IDDQ test, novel test methods, effectiveness of test methods, fault models and ATPG, and DPPM prediction
SoC/IP testing strategies Design methodologies dealing with the link between testability and manufacturing
Hardware/software co-verification
Advanced methodologies, testbenches, and flows (e.g., UVM, HDLs, HVLs)
Formal and semi-formal verification and validation techniques
Safety and security in verification and validation New methods and tools supporting functional safety and security
Self-checking testbenches in analog verification
Any other topics related to design test and verification
Emerging Device and Process Technologies and Applications (EDPT)
Design, simulation and modeling of emerging technologies
Design, simulation and modeling of emerging non-volatile memory and logic, such as STT-RAM, PC-RAM, R-RAM, and Memristors
Application of emerging devices for storage and computation including but not limited to cognitive, neuromorphic, or quantum computing
Qubit technologies and quantum computing Specialty technologies such as MEMs, NEMs
Novel or emerging solid state nanoelectronic devices and concepts
Design and Technology Co-Optimization
Optimization-based methodologies that address the interaction between design (custom, semi-custom, ASIC, FPGA, RF, memory, etc.)
Advanced-node manufacturing techniques such as multiple patterning, EUV lithography, DSA lithography,
Advanced interconnect (e.g., air gap for local interconnect, Si photonics, etc.).
Modeling, analysis, and optimization of technology implications on performance metrics like power consumption, timing, area, and cost.
Design methods and tools to improve yield and manufacturability.
Any other topics related to emerging device technologies and applications
Circuit Design, 3D Integration and Advanced Packaging (ICAP)
Low power, high-performance, and robust design of logic, memory, analog, interconnect, RF, programmable logic, and FPGA circuits
Techniques for leakage control, power optimization, and power management
Analog circuit design including but not limited to all-digital PLLs and DLLs, ADC's and DAC's
Adaptive and resilient digital circuits and systems
On-chip process, voltage, temperature, and aging sensors and monitoring
Hardware design for IoT sensors and actuators including digital logic, memory design, wireless communications, energy harvesting, signal processing, and power management
Innovative packaging technologies including 3D IC, 2.5D or interposer, and multi-chip module and their impact on system design
Design techniques, methodologies and flows for vertically integrated circuits/chips
Modeling and mitigation of device interactions for 3D ICs
Design of die-to-die interfaces in 3D/2.5D ICs
Design-for-testability and system-level design issues in 3D/2.5D
Die-package co-design
Any other topics related to circuit design, 3D integration and advanced packaging
System-level Design and Methodologies (SDM)
Methods and tools aiming at quality of systems including multi-core processors, graphics processors embedded systems, SoC, novel accelerator designs, and heterogeneous architecture designs
System-level trade-off analysis and multi-objective (e.g. yield, power, delay, area, etc.) optimization
System level power and thermal management
Exploration of influence of emerging technologies on the system level design
System level modeling and simulation to characterize effects of process, voltage, temperature, and aging on power, performance, and reliability
Cyber-Physical Systems – Design, Methodologies & Tools
HW/SW co-design, co-simulation, co-optimization, and co-exploration
HW/SW prototyping and emulation on FPGAs
Micro-architectural transformation
System communication architecture
Application driven heterogeneous computing platforms
Network-on-chip design methodologies
Any other topics related to system level design and methodologies
Cognitive Computing Hardware (CCH)
Neuromorphic computing and non-Von Neumann architectures
Hardware and architecture for neural networks and system-level design for (deep) neural computing Neural network acceleration techniques including GPGPU, FPGA and dedicated ASICs
Safe and secure machine learning Hardware accelerators for Artificial Intelligence Cognitive-inspired computing fundamentals
Cognitive-inspired computing systems
Cognitive-inspired computing with big data
Cognitive-inspired intelligent interaction AI-assisted cognitive computing approaches
Brain analysis for cognitive-inspired computing Internet of cognitive Things
Cognitive environment, sensing and data
Cognitive robots and agents Security issue in cognitive-inspired computing
Test-bed, prototype implementation and applications
Any other topics related to cognitive computing hardware

Overview

This ranking presents a comprehensive evaluation of scientific conferences in the field of Engineering and Technology. Developed by Research.com, a leading platform in science research renowned for providing trusted data on scientific contributions since 2014, the ranking offers insight into the most influential conferences based on meticulous bibliometric analysis.

Each conference's position in the ranking is determined using a unique bibliometric score formulated by Research.com. This score considers the estimated h-index and the number of leading scientists who have presented at the conference during the most recent three years. The Impact Score values incorporated in this ranking were gathered on 2024-11-27, ensuring the most current and relevant metrics.

The process of establishing the ranking involved the thorough examination of more than 2,262 conferences, selected through a detailed inspection and rigorous analysis of over 26,934 scientific documents. These works were authored or co-authored in the past three years by 9,385 leading and well-respected scientists specializing in Engineering and Technology. This extensive review guarantees that only conferences of genuine significance and scientific standing are represented.

The methodology underlying the computation of ranking scores integrates advanced, data-driven approaches and reflects the depth of scholarly research conducted by domain experts. For full details regarding the ranking procedures and the bibliometric score calculation, please visit our Methodology Page.

Papers citation over time

A key indicator for each conference is its effectiveness in reaching other researchers with the papers published at that venue.

The chart below presents the interquartile range (first quartile 25%, median 50% and third quartile 75%) of the number of citations of articles over time.

The top authors publishing at International Symposium on Quality Electronic Design (based on the number of publications) are:

  • Saraju P. Mohanty (22 papers) published 1 paper at the last edition, 1 less than at the previous edition,
  • Massoud Pedram (14 papers) published 3 papers at the last edition the same number as at the previous edition,
  • Elias Kougianos (13 papers) published 1 paper at the last edition, 1 less than at the previous edition,
  • Andrew B. Kahng (12 papers) published 1 paper at the last edition, 1 less than at the previous edition,
  • Rouwaida Kanj (11 papers) published 1 paper at the last edition, 1 less than at the previous edition.

The overall trend for top authors publishing at this conference is outlined below. The chart shows the number of publications at each edition of the conference for top authors.

Only papers with recognized affiliations are considered

The top affiliations publishing at International Symposium on Quality Electronic Design (based on the number of publications) are:

  • Tsinghua University (37 papers) published 1 paper at the last edition the same number as at the previous edition,
  • IBM (35 papers) published 2 papers at the last edition, 2 less than at the previous edition,
  • Synopsys (30 papers) published 2 papers at the last edition, 1 more than at the previous edition,
  • Georgia Institute of Technology (27 papers) published 2 papers at the last edition, 1 less than at the previous edition,
  • Intel (23 papers) published 2 papers at the last edition, 1 less than at the previous edition.

The overall trend for top affiliations publishing at this conference is outlined below. The chart shows the number of publications at each edition of the conference for top affiliations.

Publication chance based on affiliation

The publication chance index shows the ratio of articles published by the best research institutions at the conference edition to all articles published within that conference. The best research institutions were selected based on the largest number of articles published during all editions of the conference.

The chart below presents the percentage ratio of articles from top institutions (based on their ranking of total papers).Top affiliations were grouped by their rank into the following tiers: top 1-10, top 11-20, top 21-50, and top 51+. Only articles with a recognized affiliation are considered.

During the most recent 2015 edition, 3.64% of publications had an unrecognized affiliation. Out of the publications with recognized affiliations, 18.87% were posted by at least one author from the top 10 institutions publishing at the conference. Another 12.26% included authors affiliated with research institutions from the top 11-20 affiliations. Institutions from the 21-50 range included 17.92% of all publications and 50.94% were from other institutions.

Returning Authors Index

A very common phenomenon observed among researchers publishing scientific articles is the intentional selection of conferences they have already attended in the past. In particular, it is worth analyzing the case when the authors participate in the same conference from year to year.

The Returning Authors Index presented below illustrates the ratio of authors who participated in both a given as well as the previous edition of the conference in relation to all participants in a given year.

Returning Institution Index

The graph below shows the Returning Institution Index, illustrating the ratio of institutions that participated in both a given and the previous edition of the conference in relation to all affiliations present in a given year.

The experience to innovation index

Our experience to innovation index was created to show a cross-section of the experience level of authors publishing at a conference. The index includes the authors publishing at the last edition of a conference, grouped by total number of publications throughout their academic career (P) and the total number of citations of these publications ever received (C).

The group intervals were selected empirically to best show the diversity of the authors' experiences, their labels were selected as a convenience, not as judgment. The authors were divided into the following groups:

  • Novice - P < 5 or C < 25 (the number of publications less than 5 or the number of citations less than 25),
  • Competent - P < 10 or C < 100 (the number of publications less than 10 or the number of citations less than 100),
  • Experienced - P < 25 or C < 625 (the number of publications less than 25 or the number of citations less than 625),
  • Master - P < 50 or C < 2500 (the number of publications less than 50 or the number of citations less than 2500),
  • Star - P ≥ 50 and C ≥ 2500 (both the number of publications greater than 50 and the number of citations greater than 2500).

The chart below illustrates experience levels of first authors in cases of publications with multiple authors.

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