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Thomas Toifl

Thomas Toifl

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
32
Citations
4080
World Ranking
6340
National Ranking
2088

Overview

Thomas Toifl is affiliated with IBM Research - Zurich in Switzerland. Their work primarily spans the fields of Engineering and Computer Science, with a focus on Electrical and Electronic Engineering as well as Hardware and Architecture.

The main topics reflected in their research output include:

  • 3D IC and TSV technologies
  • VLSI and Analog Circuit Testing
  • Electromagnetic Compatibility and Noise Suppression

Toifl has published at least one paper in a notable venue related to integrated circuits and electronics engineering. The publication is:

  • "F4: Paving the Way to 200Gb/s Transceivers," 2022 IEEE International Solid-State Circuits Conference (ISSCC), 2022

This paper has zero citations as of the current data.

Frequent collaborators in their research include:

  • Mike Li
  • San José
  • C. Patrick Yue
  • Sudip Shekhar
  • Bo Zhang

Toifl's research contributions involve the development and examination of advanced circuit technologies and testing methodologies, as reflected by their involvement in topics like VLSI testing and noise suppression in electronics.

The publication venue associated with their recent work, the IEEE International Solid-State Circuits Conference (ISSCC), is a specialized forum for developments in solid-state circuits and systems.

Best Publications

  • A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

    L. Kull;T. Toifl;M. Schmatz;P. A. Francese

  • A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

    J. F. Bulzacchelli;C. Menolfi;T. J. Beukema;D. W. Storaska

  • 22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS

    Lukas Kull;Thomas Toifl;Martin Schmatz;Pier Andrea Francese

  • A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With $≪ -$ 16 dB Return Loss Over 10 GHz Bandwidth

    M. Kossel;C. Menolfi;J. Weiss;P. Buchmann

  • 4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm 2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS

    Toke Meyer Andersen;Florian Krismer;Johann Walter Kolar;Thomas Toifl

  • A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology

    T. Toifl;C. Menolfi;M. Ruegg;R. Reutemann

  • A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS

    Thomas Toifl;Christian Menolfi;Michael Ruegg;Robert Reutemann

  • A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

    Lukas Kull;Danny Luu;Christian Menolfi;Matthias Brandli

  • High-density optical interconnects within large-scale systems

    Christoph Berger;Marcel A. Kossel;Christian Menolfi;Thomas Morf

  • A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI

    C. Menolfi;T. Toifl;P. Buchmann;M. Kossel

  • A 4.6W/mm 2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS

    T. M. Andersen;F. Krismer;J. W. Kolar;T. Toifl

  • A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS

    Unknown

  • 30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

    F. Ellinger;L.C. Rodoni;G. Sialm;C. Kromer

  • A radiation tolerant gigabit serializer for LHC data transmission

    P Moreira;A Marchioro;J P Cachemiche;Thomas H Toifl

  • Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

    Lukas Kull;Jan Pliva;Thomas Toifl;Martin Schmatz

  • A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS

    T. Toifl;C. Menolfi;M. Ruegg;R. Reutemann

  • A 0.94-ps-RMS-jitter 0.016-mm/sup 2/ 2.5-GHz multiphase generator PLL with 360/spl deg/ digitally programmable phase shift for 10-Gb/s serial links

    T. Toifl;C. Menolfi;P. Buchmann;M. Kossel

  • 28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET

    Lukas Kull;Danny Luu;Christian Menolfi;Matthias Braendli

  • G-link and gigabit Ethernet compliant serializer for LHC data transmission

    P. Moreira;T. Toifl;A. Kluge;G. Cervelli

  • A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

    Ilter Ozkaya;Alessandro Cevrero;Pier Andrea Francese;Christian Menolfi

  • Phase locked loop apparatus with adjustable phase shift

    Christian Ivo Menolfi;Thomas Helmut Toifl

  • A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

    Christian Menoifi;Matthias Braendli;Pier Andrea Francese;Thomas Morf

  • Systems and arrangements for clock and data recovery in communications

    Hayden C. Cranford;Daniel J. Friedman;Mounir Meghelli;Thomas H. Toifl

Frequent Co-Authors

Christian Menolfi
Christian Menolfi IBM (Switzerland)
Thomas Morf
Thomas Morf IBM (United States)
Yusuf Leblebici
Yusuf Leblebici École Polytechnique Fédérale de Lausanne
Andreas Burg
Andreas Burg École Polytechnique Fédérale de Lausanne
Christoph Hagleitner
Christoph Hagleitner IBM (United States)
Daniel M. Kuchta
Daniel M. Kuchta IBM (United States)
Frank Ellinger
Frank Ellinger TU Dresden
Michel Despont
Michel Despont Swiss Center for Electronics and Microtechnology (Switzerland)

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