World's Best Scientists 2026 revealed!
Warren J. Gross

Warren J. Gross

D-Index & Metrics

Computer Science

D-Index
52
Citations
10540
World Ranking
5098
National Ranking
201

Overview

Warren J. Gross is affiliated with McGill University in Canada and has a significant body of research primarily in the fields of Computer Science and Engineering. Their work spans a broad range of subfields including Artificial Intelligence, Electrical and Electronic Engineering, Computer Networks and Communications, Computer Vision and Pattern Recognition, and Molecular Biology.

The scientist's research focuses extensively on topics such as Error Correcting Code Techniques, Advanced Wireless Communication Techniques, Coding Theory and Cryptography, Advanced Neural Network Applications, Cooperative Communication and Network Coding, DNA and Biological Computing, and Domain Adaptation and Few-Shot Learning.

Recent notable papers include:

  • High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND, 2022, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Practical Dynamic SC-Flip Polar Decoders: Algorithm and Implementation, 2020, IEEE Transactions on Signal Processing
  • Introduction to Dynamic Stochastic Computing, 2020, IEEE Circuits and Systems Magazine
  • Efficient Fine-Tuning of BERT Models on the Edge, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS)
  • A Design Framework for Invertible Logic, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Frequent co-authors collaborating with this scientist include:

  • Brett H. Meyer
  • James J. Clark
  • Marwan Jalaleddine
  • Huayi Zhou
  • Syed Mohsin Abbas

Publications are often found in these venues:

  • arXiv (Cornell University)
  • Journal of Signal Processing Systems
  • IEEE Communications Letters
  • IEEE Access
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Best Publications

  • Deep Learning Methods for Improved Decoding of Linear Codes

    Eliya Nachmani;Elad Marciano;Loren Lugosch;Warren J. Gross

  • Fast Polar Decoders: Algorithm and Implementation

    Gabi Sarkis;Pascal Giard;Alexander Vardy;Claude Thibeault

  • A Semi-Parallel Successive-Cancellation Decoder for Polar Codes

    C. Leroux;A. J. Raymond;G. Sarkis;W. J. Gross

  • Hardware architectures for successive cancellation decoding of polar codes

    Camille Leroux;Ido Tal;Alexander Vardy;Warren J. Gross

  • VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

    Arash Ardakani;Francois Leduc-Primeau;Naoya Onizawa;Takahiro Hanyu

  • Fully Parallel Stochastic LDPC Decoders

    S. Sharifi Tehrani;S. Mannor;W.J. Gross

  • Fast List Decoders for Polar Codes

    Gabi Sarkis;Pascal Giard;Alexander Vardy;Claude Thibeault

  • Fast and Flexible Successive-Cancellation List Decoders for Polar Codes

    Seyyed Ali Hashemi;Carlo Condo;Warren J. Gross

  • Stochastic decoding of LDPC codes

    S. Sharifi Tehrani;W.J. Gross;S. Mannor

  • Simplified MAP algorithm suitable for implementation of turbo decoders

    W.J. Gross;P.G. Gulak

  • Delayed Stochastic Decoding of LDPC Codes

    A. Naderi;S. Mannor;M. Sawan;W. J. Gross

  • Hardware Architecture for List Successive Cancellation Decoding of Polar Codes

    Alexios Balatsoukas-Stimming;Alexandre J. Raymond;Warren J. Gross;Andreas Burg

  • Majority-Based Tracking Forecast Memories for Stochastic LDPC Decoding

    Saeed Sharifi Tehrani;Ali Naderi;Guy-Armand Kamendje;Saied Hemati

  • VLSI architectures for the MAP algorithm

    E. Boutillon;W.J. Gross;P.G. Gulak

  • Neural offset min-sum decoding

    Loren Lugosch;Warren J. Gross

  • Increasing the Throughput of Polar Decoders

    Gabi Sarkis;Warren J. Gross

  • Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes

    Gabi Sarkis;Ido Tal;Pascal Giard;Alexander Vardy

  • Methods and systems for decoding polar codes

    Warren Gross;Gabi Sarkis;Alexandre Raymond;Camille Leroux

  • A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS

    A. Mishra;A. J. Raymond;L. G. Amaru;G. Sarkis

  • Hardware Implementation of Successive-Cancellation Decoders for Polar Codes

    Camille Leroux;Alexandre J. Raymond;Gabi Sarkis;Ido Tal

  • An Architecture to Accelerate Convolution in Deep Neural Networks

    Arash Ardakani;Carlo Condo;Mehdi Ahmadi;Warren J. Gross

Frequent Co-Authors

Takahiro Hanyu
Takahiro Hanyu Tohoku University
Shie Mannor
Shie Mannor Technion – Israel Institute of Technology
Alexander Vardy
Alexander Vardy University of California, San Diego
Frank R. Kschischang
Frank R. Kschischang University of Toronto
P.G. Gulak
P.G. Gulak University of Toronto
Andreas Burg
Andreas Burg École Polytechnique Fédérale de Lausanne
Xiaohu You
Xiaohu You Southeast University
Zaichen Zhang
Zaichen Zhang Southeast University
Ralf Koetter
Ralf Koetter Technical University of Munich
Michael Rabbat
Michael Rabbat Facebook (United States)

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