Lukas Sekanina

Best Publications

• EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods

  Vojtech Mrazek;Radek Hrbacek;Zdenek Vasicek;Lukas Sekanina

  345
  Citations

• Design of power-efficient approximate multipliers for approximate artificial neural networks

  Vojtech Mrazek;Syed Shakib Sarwar;Lukas Sekanina;Zdenek Vasicek

  173
  Citations

• Efficient recognition of speed limit signs

  J. Torresen;J.W. Bakke;L. Sekanina

  157
  Citations

• Evolutionary Approach to Approximate Digital Circuits Design

  Zdenek Vasicek;Lukas Sekanina

  153
  Citations

• Virtual reconfigurable circuits for real-world applications of evolvable hardware

  Lukáš Sekanina

  148
  Citations

• Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers

  Mohammad Saeed Ansari;Vojtech Mrazek;Bruce F. Cockburn;Lukas Sekanina

  129
  Citations

• ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining

  Vojtech Mrazek;Zdenek Vasicek;Lukas Sekanina;Muhammad Abdullah Hanif

  119
  Citations

• Novel Hardware Implementation of Adaptive Median Filters

  Z. Vasicek;L. Sekanina

  86
  Citations

• Image Filter Design with Evolvable Hardware

  Lukás Sekanina

  78
  Citations

• An evolvable hardware system in Xilinx Virtex II Pro FPGA

  Zdenek Vasicek;Lukas Sekanina

  77
  Citations

• Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing

  R. Salvador;A. Otero;J. Mora;E. de la Torre

  71
  Citations

• An Evolvable Combinational Unit for FPGAs

  Lukáš Sekanina;Štěpán Friedl

  70
  Citations

• Towards evolvable systems based on the Xilinx Zynq platform

  Roland Dobai;Lukas Sekanina

  67
  Citations

• Physical Demonstration of Polymorphic Self-Checking Circuits

  R. Ruzicka;L. Sekanina;R. Prokop

  63
  Citations

• Evolutionary design of gate-level polymorphic digital circuits

  Lukáš Sekanina

  63
  Citations

• Evolutionary Design of Arbitrarily Large Sorting Networks Using Development

  Lukáš Sekanina;Michal Bidlo

  63
  Citations

• Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware

  Zdenek Vasicek;Lukas Sekanina

  62
  Citations

• Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators

  Vojtech Mrazek;Lukas Sekanina;Zdenek Vasicek

  58
  Citations

• Towards evolvable IP cores for FPGAs

  L. Sekanina

  58
  Citations

• An evolvable image filter: experimental evaluation of a complete hardware implementation in FPGA

  Tomáš Martínek;Lukáš Sekanina

  57
  Citations