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International Solid-State Circuits Conference

International Solid-State Circuits Conference (ISSCC)

Name: International Solid-State Circuits Conference
Start: 2023-02-19
End: 2023-02-23
Location: San Francisco

Location: San Francisco , United States

Conference dates: 2/19/2023 - 2/23/2023

Research H-index

Official website

Ranking & Metrics

Discipline name	Position	Best Scientists	Publications	D-Index
Materials Science	4	35	46	14
Electronics and Electrical Engineering	4	213	550	42
Engineering and Technology	27	13	17	10

Call for Papers

ISSCC is interested in innovation in solid-state circuits more than ever! This year, authors are invited to submit papers on work that is beyond the conventional areas covered in solid-state circuit conferences and has potential to open up new areas for IC research and development. The submitted work needs to be supported by experimental evidence that shows the feasibility in hardware. The papers will be reviewed by the Technology Directions subcommittee. The accepted papers will be presented in a separate innovation session at the conference.

ANALOG: Circuits with analog-dominated innovation; amplifiers, comparators, oscillators, filters, references; nonlinear analog circuits; digitally-assisted analog circuits; Sensor interface circuits; analog circuits in sub-10nm scaled technologies

DATA CONVERTERS: Nyquist-rate and oversampling A/D and D/A converters; embedded and application-specific A/D and D/A converters; time-to-digital converters; Innovative and emerging converter architectures.

DIGITAL CIRCUITS and ARCHITECTURES & SYSTEMS*: Digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for microprocessors, micro-controllers, application processors, graphics processors, automotive processors; digital systems for communications, video and multimedia, cryptography, smart cards, security and trusted computing, accelerators, reconfigurable systems, near- and sub-threshold systems, and emerging applications. Digital circuits for intra-chip communication, clock distribution, soft-error and variation-tolerant design, power management (i.e., voltage regulators, adaptive digital circuits, digital sensors), digital PLLs for processors, neurocomputing with a focus on digital-circuit techniques, and security circuits (i.e., PUFs, TRNGs, side-channel attack countermeasures, and attack-detection sensors).

IMAGERS, MEMS, MEDICAL, & DISPLAYS: Image sensors and SoCs; automotive, LIDAR; ultrasound and medical imaging; MEMS sensor and actuators; wearable, implantable, ingestible devices; biomedical SoCs, neural interfaces and closed-loop systems; body area networks; biosensors, microarrays; display drivers, sensing or haptic displays; sensing and displays for AR/VR.

MACHINE LEARNING and AI: Chips demonstrating system, architecture and circuit innovations for machine learning and artificial intelligence: SoCs, chiplets, multi-chip solutions, processor architectures, accelerators and analog/digital circuits; near-sensor and in-sensor processing schemes; all architectures and circuits leveraging near-memory and in-memory computation with system and SOC level innovations for AI using volatile or non-volatile memories. Hardware optimizations for new ML models including transformers, graph neural networks, hyper-dimensional computing, spiking neural networks and applications including mobile, wearables, data centers and autonomous driving, etc.

MEMORY: Macros for near-memory compute and in-memory-compute across various applications; Static, dynamic, and non-volatile memories for stand-alone and embedded applications; memory/SSD controllers; high bandwidth I/O interfaces for memory; memories based on phase-change, magnetic, spin-transfer-torque, ferroelectric, and resistive materials; array architectures and circuits to improve low-voltage operation, power reduction, reliability, and fault tolerance; 3D memory circuits for memory-memory and memory-logic stacking; error correction and yield enhancement schemes for memories; application-specific circuit enhancements within the memory subsystem.

POWER MANAGEMENT: Power management and control circuits, regulators; switched-mode power converter ICs using inductive, capacitive, and hybrid techniques; energy harvesting circuits and systems; wide-bandgap topologies and gate-drivers; power and signal isolators; robust power management circuits for automotive and other harsh environments; circuits for lighting, wireless power and envelope modulators.

RF CIRCUITS and WIRELESS SYSTEMS**: Building blocks and complete solutions at RF, mm-Wave and THz frequencies for receivers, transmitters, frequency synthesizers, RF filters, transceivers, SoCs, and SiPs. Innovative circuit, system and packaging solutions for established wireless standards as well as future systems or applications, such as radar, sensing and imaging and those improving spectral and energy efficiency.

TECHNOLOGY DIRECTIONS: Emerging and novel IC, system, and device solutions in various areas such as integrated photonics, silicon electronics-photonics integration, optical phased and focal plane arrays; quantum devices for metrology, computing, etc.; flexible, stretchable, foldable, printable, and 3D electronic systems; biomedical sensors for cellular and molecular targets; wireless power transfer at-distance (e.g., RF and mm-wave, optical, ultrasonic); novel platforms for non-CMOS computing and machine learning; integrated meta-materials, circuits in alternative device platforms (e.g., carbon, organic, superconductor, spin, etc.).

WIRELINE: Receivers/transmitters/transceivers for wireline systems, including backplane transceivers, copper-cable links, chip-to-chip communications, 2.5/3D interconnect, on-chip links, optical links, and silicon photonics; exploratory I/O circuits for advancing data rates, bandwidth density, power efficiency, equalization, robustness, adaptation capability, and design methodology; building blocks for wireline transceivers (including but not limited to AGCs, analog and ADC/DAC-based front ends, TIAs, equalizers, clock generation and distribution circuits including PLLs, clock recovery, line drivers, and hybrids).

Overview

This comprehensive ranking presents a curated list of scientific conferences in the field of Engineering and Technology, offering a reliable resource for researchers, practitioners, and academics seeking authoritative venues for scholarly exchange. The ranking has been meticulously developed by Research.com, a recognized leader in the dissemination of scientific research data across all major disciplines, including Engineering and Technology. Since 2014, Research.com has provided the global academic community with trusted insights into scientific contributions, continuously setting high standards in research analytics.

The evaluations featured on this page are grounded in a proprietary bibliometric score devised by Research.com. This score is calculated using an advanced method that incorporates both the estimated h-index and the count of leading scientists who have participated in each conference within the preceding three years. Such a comprehensive approach ensures the recognition of conferences that consistently attract top-tier scientific contributions and renowned experts in the domain.

The ranking is based on Impact Score values that were compiled as of 2024-11-27, reflecting the most current data and developments within the field. To ensure accuracy and rigor, the ranking process entailed the assessment of more than 2,262 conferences. These venues were selected after an exhaustive review entailing the examination of over 26,934 scientific documents published over the past three years by 9,385 distinguished and highly respected scientists specializing in Engineering and Technology.

For a detailed explanation of the methodology used to determine the ranking scores and to understand the analytical framework underpinning this assessment, please refer to our Methodology Page.

Papers citation over time

A key indicator for each conference is its effectiveness in reaching other researchers with the papers published at that venue.

The chart below presents the interquartile range (first quartile 25%, median 50% and third quartile 75%) of the number of citations of articles over time.

Top authors and change over time

The top authors publishing at International Solid-State Circuits Conference (based on the number of publications) are:

Kofi A. A. Makinwa (45 papers) published 7 papers at the last edition, 4 more than at the previous edition,
Anantha P. Chandrakasan (42 papers) published 1 paper at the last edition the same number as at the previous edition,
Dennis Sylvester (39 papers) published 2 papers at the last edition the same number as at the previous edition,
David Blaauw (37 papers) published 2 papers at the last edition the same number as at the previous edition,
Hoi-Jun Yoo (30 papers) absent at the last edition.

The overall trend for top authors publishing at this conference is outlined below. The chart shows the number of publications at each edition of the conference for top authors.

Top affiliations and change over time

Only papers with recognized affiliations are considered

The top affiliations publishing at International Solid-State Circuits Conference (based on the number of publications) are:

Intel (173 papers) published 22 papers at the last edition, 11 more than at the previous edition,
Samsung (152 papers) published 29 papers at the last edition, 12 more than at the previous edition,
IBM (120 papers) published 8 papers at the last edition, 6 more than at the previous edition,
Katholieke Universiteit Leuven (110 papers) published 9 papers at the last edition, 3 more than at the previous edition,
KAIST (102 papers) published 11 papers at the last edition, 5 more than at the previous edition.

The overall trend for top affiliations publishing at this conference is outlined below. The chart shows the number of publications at each edition of the conference for top affiliations.

Publication chance based on affiliation

The publication chance index shows the ratio of articles published by the best research institutions at the conference edition to all articles published within that conference. The best research institutions were selected based on the largest number of articles published during all editions of the conference.

The chart below presents the percentage ratio of articles from top institutions (based on their ranking of total papers).Top affiliations were grouped by their rank into the following tiers: top 1-10, top 11-20, top 21-50, and top 51+. Only articles with a recognized affiliation are considered.

During the most recent 2021 edition, 5.49% of publications had an unrecognized affiliation. Out of the publications with recognized affiliations, 39.42% were posted by at least one author from the top 10 institutions publishing at the conference. Another 12.86% included authors affiliated with research institutions from the top 11-20 affiliations. Institutions from the 21-50 range included 27.39% of all publications and 20.33% were from other institutions.

Returning Authors Index

A very common phenomenon observed among researchers publishing scientific articles is the intentional selection of conferences they have already attended in the past. In particular, it is worth analyzing the case when the authors participate in the same conference from year to year.

The Returning Authors Index presented below illustrates the ratio of authors who participated in both a given as well as the previous edition of the conference in relation to all participants in a given year.

Returning Institution Index

The graph below shows the Returning Institution Index, illustrating the ratio of institutions that participated in both a given and the previous edition of the conference in relation to all affiliations present in a given year.

The experience to innovation index

Our experience to innovation index was created to show a cross-section of the experience level of authors publishing at a conference. The index includes the authors publishing at the last edition of a conference, grouped by total number of publications throughout their academic career (P) and the total number of citations of these publications ever received (C).

The group intervals were selected empirically to best show the diversity of the authors' experiences, their labels were selected as a convenience, not as judgment. The authors were divided into the following groups:

Novice - P < 5 or C < 25 (the number of publications less than 5 or the number of citations less than 25),
Competent - P < 10 or C < 100 (the number of publications less than 10 or the number of citations less than 100),
Experienced - P < 25 or C < 625 (the number of publications less than 25 or the number of citations less than 625),
Master - P < 50 or C < 2500 (the number of publications less than 50 or the number of citations less than 2500),
Star - P ≥ 50 and C ≥ 2500 (both the number of publications greater than 50 and the number of citations greater than 2500).

The chart below illustrates experience levels of first authors in cases of publications with multiple authors.

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