S. Deleonibus

Best Publications

• Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performance

  F. Mayer;C. Le Royer;J.-F. Damlencourt;K. Romanjek

  355
  Citations

• Advances, challenges and opportunities in 3D CMOS sequential integration

  P. Batude;M. Vinet;B. Previtali;C. Tabone

  325
  Citations

• Advances in 3D CMOS sequential integration

  P. Batude;M. Vinet;A. Pouydebasque;C. Le Royer

  304
  Citations

• Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

  O. Faynot;F. Andrieu;O. Weber;C. Fenouillet-Beranger

  237
  Citations

• 3D monolithic integration: Technological challenges and electrical results

  M. Vinet;P. Batude;C. Tabone;B. Previtali

  235
  Citations

• High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

  O. Weber;O. Faynot;F. Andrieu;C. Buj-Dufournet

  214
  Citations

• Engineered substrates for future More Moore and More than Moore integrated devices

  L. Clavelier;C. Deguet;L. Di Cioccio;E. Augendre

  192
  Citations

• Lateral interband tunneling transistor in silicon-on-insulator

  C. Aydin;A. Zaslavsky;S. Luryi;S. Cristoloveanu

  189
  Citations

• 15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

  C. Dupre;A. Hubert;S. Becu;M. Jublot

  185
  Citations

• 3D monolithic integration

  P. Batude;M. Vinet;A. Pouydebasque;C. Le Royer

  181
  Citations

• Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

  E. Bernard;T. Ernst;B. Guillaumot;N. Vulliet

  176
  Citations

• Multiple gate devices: advantages and challenges

  T. Poiroux;M. Vinet;O. Faynot;J. Widiez

  170
  Citations

• FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

  C. Fenouillet-Beranger;S. Denorme;P. Perreau;C. Buj

  167
  Citations

• Bonded planar double-metal-gate NMOS transistors down to 10 nm

  M. Vinet;T. Poiroux;J. Widiez;J. Lolivier

  153
  Citations

• 75 nm damascene metal gate and high-k integration for advanced CMOS devices

  B. Guillaumot;X. Garros;F. Lime;K. Oshima

  134
  Citations

• Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)

  Barbara De Salvo;C. Gerardi;R. van Schaijk;S.A. Lombardo

  129
  Citations

• How far will silicon nanocrystals push the scaling limits of NVMs technologies

  B. De Salvo;C. Gerardi;S. Lombardo;T. Baron

  120
  Citations

• Individual charge traps in silicon nanowires. Measurements of location, spin and occupation number by Coulomb blockade spectroscopy

  M. Hofheinz;X. Jehl;M. Sanquer;G. Molas

  109
  Citations

• Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance

  Unknown

  96
  Citations

• Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO 2 gate stack

  V. Barral;T. Poiroux;F. Andrieu;C. Buj-Dufournet

  92
  Citations