Pascal Vivet

Best Publications

• An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework

  Unknown

  236
  Citations

• Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook

  Unknown

  199
  Citations

• A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller

  Unknown

  170
  Citations

• A 477mW NoC-based digital baseband for MIMO 4G SDR

  Fabien Clermidy;Christian Bernard;Romain Lemaire;Jerome Martin

  128
  Citations

• A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip

  Unknown

  119
  Citations

• A fully-asynchronous low-power framework for GALS NoC integration

  Unknown

  116
  Citations

• IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management

  Unknown

  113
  Citations

• An Asynchronous Power Aware and Adaptive NoC Based Circuit

  Unknown

  94
  Citations

• Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC

  Unknown

  92
  Citations

• Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture

  Unknown

  87
  Citations

• 3D Sequential Integration: Application-driven technological achievements and guidelines

  P. Batude;L. Brunet;C. Fenouillet-Beranger;F. Andrieu

  81
  Citations

• A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling

  Unknown

  76
  Citations

• A fully-asynchronous low-power framework for GALS NoC integration

  Unknown

  76
  Citations

• Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

  Unknown

  73
  Citations

• A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC

  Unknown

  65
  Citations

• Design and Implementation of a GALS Adapter for ANoC Based Architectures

  Unknown

  64
  Citations

• Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures

  Unknown

  63
  Citations

• A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip

  Unknown

  61
  Citations

• Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture

  Unknown

  57
  Citations

• 2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters

  Unknown

  56
  Citations