World's Best Scientists 2026 revealed!
IEEE

VLSI Design (VLSID) (VLSID)

Location: HICC, Hyderabad , India

Submission deadline: 7/31/2022

Conference dates: 1/8/2023 - 1/12/2023

Research H-index
5

Ranking & Metrics

Discipline name Position Best Scientists Publications D-Index
Electronics and Electrical Engineering 395 29 37 5

Call for Papers

VLSID 2023 will be hosted in the best stand-alone convention center, HICC Hyderabad. The city is home to some of the best universities, top global companies in research and manufacturing, strong defense sector and thriving start-ups. Hyderabad has a rich culture with numerous historic places to visit and world famous Hyderabad Biryani to cherish. We look forward to hosting and giving you the best experience at the conference. We encourage your participation to the conference and call you to be part of the exciting know-how’s of the industry and spend quality time exploring Hyderabad.
TOPICS
Hardware for AI and ML:
Chips demonstrating system, architecture and circuit innovations for machine learning and artificial intelligence, AI accelerator design, AI boosted circuits and systems for Brain Machine Interface, Memory Centric Accelerator Design, Low power autonomous systems.
Embedded Systems Design:
ESL, System-level design methodology, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect Tolerant Architectures, Hardware/Software Co-Design & Verification, Reconfigurable Computing, Embedded Multicores SOC and Systems, Embedded Software Including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip, Embedded for automotive and Electric Vehicles
Analog & Mixed Signal circuits:
Amplifiers, comparators, oscillators, filters, references; nonlinear analog circuits; digitally-assisted analog circuits; Analog design at lower technology nodes, Analog Circuits for Various Applications, Data Converters, High Speed Interfaces.
Low power Digital Architectures:
Next generation Digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for reduced power and form factor, near- and sub-threshold systems, emerging applications, Digital circuits for intra-chip communication, clock distribution, variation-tolerant design, digital regulators and digital sensors.
Photonic Integrated Circuits:
Silicon and III-V Photonic Integrated Circuits, Waveguides/interconnects, On-chip lasers, Optical Multiplexers/Demultiplexers, Photo detectors and sensors, Quantum photonics, RF Photonics, Mid-IR/THz Photonics, Heterogeneous integration, Packaging of Photonic devices, Quantum photonics, RF Photonics, Mid-IR and THz Photonics.
Advances in CAD for VLSI:
Logic and behavioural synthesis, logic mapping, simulation and formal verification, physical design techniques, post route optimizations, simulation Tools for Design Verification, Static Timing and Timing Exceptions, Mixed Signal Simulations in sub 10 nm nodes.
RF Circuits and Wireless systems:
RF, mm-Wave and THz transceivers, SoCs, and SiPs. frequency synthesizers, system architecture for 5G and 6G wireless, next generation systems for radar, sensing, and imaging. Reliability aspects in RFICs.
Latest trends in device design and modelling:
Deep nanoscale CMOS devices, device modeling and simulation, multi-domain simulation, device/circuit-level reliability and variability, Devices for beyond CMOS, compact modeling and novel TCAD solutions.
Wireline and Optical Communication Circuits and Systems:
Receivers/transmitters/transceivers for wireline systems, exploratory I/O circuits for advancing data rates, bandwidth density, power efficiency, equalization, robustness, adaptation capability, and design methodology; building blocks for wireline transceivers (such as AGCs, analog and ADC/DAC-based front ends, equalizers, clock generation and distribution circuits including PLLs, line drivers, and hybrids).
Beyond 2D in Packaging and interconnects:
Wafer-level packaging, embedded chip packaging, 2.5D/3D integration, Silicon, SiC & Glass interposer, Thermal characterization and simulation, component, system and product level thermal management and characterization, Au/Ag/Cu/Al Wire-bond / Wedge bond technology, Flip-chip & Cu pillar, Solder alternatives, Cu to Cu, wafer-level bonding & die attachment (Pb-free), Fan-out, panel-level, chiplets, SiP, micro-bump, high I/O thermocompression/hybrid bonding, fine-pitch/multi-layer RDL, printable interconnects.
Sensors interfacing circuits and systems:
Sensor Interfacing, Instrumentation, Biomedical Circuits and Healthcare Systems, Low Noise Circuits, EMI Immune Design, Auto Calibration Techniques, Wearable Electronics, flexible electronics, ultra-low power circuit techniques, circuits and systems for IoT.
Power and Energy Management:
Power management and control circuits, regulators; power converter ICs, energy harvesting circuits and systems; wide-bandgap topologies and gate-drivers; power and signal isolators, Power management for automotive systems, battery management circuits and systems.
Neuromorphic Circuits and Systems:
Device, circuit, architecture design, analysis and optimization for neuromorphic computing systems, Complexity and scalability of neuromorphic computing, Emerging technologies for brain-inspired nano-computing and communication, Applications of neuromorphic computing in embedded and IoT devices, unmanned vehicles and drones, and cyber-physical systems.
Test and Reliability:
Simulation, formal verification, validation at different abstraction levels, DFT, fault modelling and simulation, ATPG, BIST, fault tolerance, post-silicon validation and debug, delay test, memory test, reliability testing.

Overview

The ranking presented on this page offers a comprehensive evaluation of scientific conferences within the domain of Computer Science. Developed by Research.com, a preeminent platform recognized for delivering trusted data and analytics on scientific contributions since 2014, this ranking is underpinned by a meticulous methodology tailored to highlight excellence and influence in computer science conference venues.

Conference positions are determined through a proprietary bibliometric score developed by Research.com. This score integrates the estimated h-index of conferences with the number of leading scientists who have contributed to each event in the preceding three years, thereby offering a nuanced measure of both scholarly impact and reputation within the scientific community. The ranking incorporates up-to-date Impact Score values collected as of 2024-11-27, ensuring data currency and relevance.

The process underpinning the ranking is characterized by remarkable scope and analytical depth. Over 2,742 conferences were systematically considered and selected following detailed scrutiny and rigorous assessment. The evaluation encompasses the analysis of more than 148,739 scientific documents, published over the last three years by a cohort of 13,184 leading and well-respected scientists active in the field of Computer Science. Such an extensive review ensures that the ranking reflects the collective scholarly output and active engagement within the discipline.

For a comprehensive understanding of the methodology employed in computing the ranking scores, including detailed criteria and calculation processes, please refer to our Methodology Page.

Papers citation over time

A key indicator for each conference is its effectiveness in reaching other researchers with the papers published at that venue.

The chart below presents the interquartile range (first quartile 25%, median 50% and third quartile 75%) of the number of citations of articles over time.

The top authors publishing at International Conference on VLSI Design (based on the number of publications) are:

  • Prabhat Mishra (10 papers) published 1 paper at the last edition, 1 less than at the previous edition,
  • S. K. Nandy (10 papers) published 5 papers at the last edition, 3 more than at the previous edition,
  • Ranjani Narayan (8 papers) published 4 papers at the last edition, 1 more than at the previous edition,
  • Kewal K. Saluja (8 papers) published 2 papers at the last edition the same number as at the previous edition,
  • Amit Patra (7 papers) absent at the last edition.

The overall trend for top authors publishing at this conference is outlined below. The chart shows the number of publications at each edition of the conference for top authors.

Only papers with recognized affiliations are considered

The top affiliations publishing at International Conference on VLSI Design (based on the number of publications) are:

  • Indian Institute of Technology Kharagpur (33 papers) published 9 papers at the last edition the same number as at the previous edition,
  • Indian Institute of Science (23 papers) published 8 papers at the last edition, 2 more than at the previous edition,
  • Indian Institute of Technology Guwahati (17 papers) published 12 papers at the last edition, 9 more than at the previous edition,
  • Indian Institute of Technology Bombay (14 papers) published 4 papers at the last edition the same number as at the previous edition,
  • IBM (14 papers) published 2 papers at the last edition, 1 less than at the previous edition.

The overall trend for top affiliations publishing at this conference is outlined below. The chart shows the number of publications at each edition of the conference for top affiliations.

Publication chance based on affiliation

The publication chance index shows the ratio of articles published by the best research institutions at the conference edition to all articles published within that conference. The best research institutions were selected based on the largest number of articles published during all editions of the conference.

The chart below presents the percentage ratio of articles from top institutions (based on their ranking of total papers).Top affiliations were grouped by their rank into the following tiers: top 1-10, top 11-20, top 21-50, and top 51+. Only articles with a recognized affiliation are considered.

During the most recent 2016 edition, 9.70% of publications had an unrecognized affiliation. Out of the publications with recognized affiliations, 37.19% were posted by at least one author from the top 10 institutions publishing at the conference. Another 18.18% included authors affiliated with research institutions from the top 11-20 affiliations. Institutions from the 21-50 range included 23.97% of all publications and 20.66% were from other institutions.

Returning Authors Index

A very common phenomenon observed among researchers publishing scientific articles is the intentional selection of conferences they have already attended in the past. In particular, it is worth analyzing the case when the authors participate in the same conference from year to year.

The Returning Authors Index presented below illustrates the ratio of authors who participated in both a given as well as the previous edition of the conference in relation to all participants in a given year.

Returning Institution Index

The graph below shows the Returning Institution Index, illustrating the ratio of institutions that participated in both a given and the previous edition of the conference in relation to all affiliations present in a given year.

The experience to innovation index

Our experience to innovation index was created to show a cross-section of the experience level of authors publishing at a conference. The index includes the authors publishing at the last edition of a conference, grouped by total number of publications throughout their academic career (P) and the total number of citations of these publications ever received (C).

The group intervals were selected empirically to best show the diversity of the authors' experiences, their labels were selected as a convenience, not as judgment. The authors were divided into the following groups:

  • Novice - P < 5 or C < 25 (the number of publications less than 5 or the number of citations less than 25),
  • Competent - P < 10 or C < 100 (the number of publications less than 10 or the number of citations less than 100),
  • Experienced - P < 25 or C < 625 (the number of publications less than 25 or the number of citations less than 625),
  • Master - P < 50 or C < 2500 (the number of publications less than 50 or the number of citations less than 2500),
  • Star - P ≥ 50 and C ≥ 2500 (both the number of publications greater than 50 and the number of citations greater than 2500).

The chart below illustrates experience levels of first authors in cases of publications with multiple authors.

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