Ranking & Metrics Conference Call for Papers Other Conferences in United States


HICC, Hyderabad, India

Submission Deadline: Sunday 31 Jul 2022

Conference Dates: Jan 08, 2023 - Jan 12, 2023

Impact Score 0.50


Conference Organizers: Deadline extended?
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Ranking & Metrics Impact Score is a novel metric devised to rank conferences based on the number of contributing the best scientists in addition to the h-index estimated from the scientific papers published by the best scientists. See more details on our methodology page.

Research Impact Score: 0.50
Contributing Best Scientists: 9
Papers published by Best Scientists 8
Research Ranking (Electronics and Electrical Engineering) 581

Conference Call for Papers

VLSID 2023 will be hosted in the best stand-alone convention center, HICC Hyderabad. The city is home to some of the best universities, top global companies in research and manufacturing, strong defense sector and thriving start-ups. Hyderabad has a rich culture with numerous historic places to visit and world famous Hyderabad Biryani to cherish. We look forward to hosting and giving you the best experience at the conference. We encourage your participation to the conference and call you to be part of the exciting know-how’s of the industry and spend quality time exploring Hyderabad.
Hardware for AI and ML:
Chips demonstrating system, architecture and circuit innovations for machine learning and artificial intelligence, AI accelerator design, AI boosted circuits and systems for Brain Machine Interface, Memory Centric Accelerator Design, Low power autonomous systems.
Embedded Systems Design:
ESL, System-level design methodology, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect Tolerant Architectures, Hardware/Software Co-Design & Verification, Reconfigurable Computing, Embedded Multicores SOC and Systems, Embedded Software Including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip, Embedded for automotive and Electric Vehicles
Analog & Mixed Signal circuits:
Amplifiers, comparators, oscillators, filters, references; nonlinear analog circuits; digitally-assisted analog circuits; Analog design at lower technology nodes, Analog Circuits for Various Applications, Data Converters, High Speed Interfaces.
Low power Digital Architectures:
Next generation Digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for reduced power and form factor, near- and sub-threshold systems, emerging applications, Digital circuits for intra-chip communication, clock distribution, variation-tolerant design, digital regulators and digital sensors.
Photonic Integrated Circuits:
Silicon and III-V Photonic Integrated Circuits, Waveguides/interconnects, On-chip lasers, Optical Multiplexers/Demultiplexers, Photo detectors and sensors, Quantum photonics, RF Photonics, Mid-IR/THz Photonics, Heterogeneous integration, Packaging of Photonic devices, Quantum photonics, RF Photonics, Mid-IR and THz Photonics.
Advances in CAD for VLSI:
Logic and behavioural synthesis, logic mapping, simulation and formal verification, physical design techniques, post route optimizations, simulation Tools for Design Verification, Static Timing and Timing Exceptions, Mixed Signal Simulations in sub 10 nm nodes.
RF Circuits and Wireless systems:
RF, mm-Wave and THz transceivers, SoCs, and SiPs. frequency synthesizers, system architecture for 5G and 6G wireless, next generation systems for radar, sensing, and imaging. Reliability aspects in RFICs.
Latest trends in device design and modelling:
Deep nanoscale CMOS devices, device modeling and simulation, multi-domain simulation, device/circuit-level reliability and variability, Devices for beyond CMOS, compact modeling and novel TCAD solutions.
Wireline and Optical Communication Circuits and Systems:
Receivers/transmitters/transceivers for wireline systems, exploratory I/O circuits for advancing data rates, bandwidth density, power efficiency, equalization, robustness, adaptation capability, and design methodology; building blocks for wireline transceivers (such as AGCs, analog and ADC/DAC-based front ends, equalizers, clock generation and distribution circuits including PLLs, line drivers, and hybrids).
Beyond 2D in Packaging and interconnects:
Wafer-level packaging, embedded chip packaging, 2.5D/3D integration, Silicon, SiC & Glass interposer, Thermal characterization and simulation, component, system and product level thermal management and characterization, Au/Ag/Cu/Al Wire-bond / Wedge bond technology, Flip-chip & Cu pillar, Solder alternatives, Cu to Cu, wafer-level bonding & die attachment (Pb-free), Fan-out, panel-level, chiplets, SiP, micro-bump, high I/O thermocompression/hybrid bonding, fine-pitch/multi-layer RDL, printable interconnects.
Sensors interfacing circuits and systems:
Sensor Interfacing, Instrumentation, Biomedical Circuits and Healthcare Systems, Low Noise Circuits, EMI Immune Design, Auto Calibration Techniques, Wearable Electronics, flexible electronics, ultra-low power circuit techniques, circuits and systems for IoT.
Power and Energy Management:
Power management and control circuits, regulators; power converter ICs, energy harvesting circuits and systems; wide-bandgap topologies and gate-drivers; power and signal isolators, Power management for automotive systems, battery management circuits and systems.
Neuromorphic Circuits and Systems:
Device, circuit, architecture design, analysis and optimization for neuromorphic computing systems, Complexity and scalability of neuromorphic computing, Emerging technologies for brain-inspired nano-computing and communication, Applications of neuromorphic computing in embedded and IoT devices, unmanned vehicles and drones, and cyber-physical systems.
Test and Reliability:
Simulation, formal verification, validation at different abstraction levels, DFT, fault modelling and simulation, ATPG, BIST, fault tolerance, post-silicon validation and debug, delay test, memory test, reliability testing.


Top Research Topics at International Conference on VLSI Design?

  • Electronic engineering (34.05%)
  • Very-large-scale integration (16.91%)
  • Embedded system (15.40%)

The aim of International Conference on VLSI Design is to expand the discussion of research in Electronic engineering, Very-large-scale integration, Embedded system, Algorithm and CMOS. The event facilitates discussions on Electronic engineering that incorporate concepts from other fields like Electronic circuit, Electrical engineering and Voltage. The works on Electrical engineering deal in particular with Transistor.

Topics in Very-large-scale integration were tackled in line with various other fields like Routing (electronic design automation) and Parallel computing. The study on Embedded system presented in the event intersects with subjects under the field of Computer architecture. Algorithm and Automatic test pattern generation are closely related fields of research discussed in the event.

Many of the studies tackled connect Automatic test pattern generation with a similar field of study like Fault coverage. The studies tackled, which mainly focus on CMOS, apply to Low-power electronics as well. The work on Logic gate presented in the event focuses on Logic synthesis in particular.

What are the most cited papers published at the conference?

  • SPARK: a high-level synthesis framework for applying parallelizing compiler transformations (360 citations)
  • Low-power wireless sensor networks (356 citations)
  • Trading Accuracy for Power with an Underdesigned Multiplier Architecture (314 citations)

Research areas of the most cited articles at International Conference on VLSI Design:

The objective of the published papers is to combine knowledge in the areas of Electronic engineering, Embedded system, Algorithm, Very-large-scale integration and CMOS. While the conference articles focused on Electronic engineering, they were also able to explore topics like Electronic circuit, Electrical engineering and Low-power electronics. The conference papers explore research in Embedded system alongside concepts in Computer architecture and other areas of study in High-level synthesis.

What topics the last edition of the conference is best known for?

  • Operating system
  • Artificial intelligence
  • Electrical engineering

The previous edition focused in particular on these issues:

International Conference on VLSI Design investigates studies in Electronic engineering, CMOS, Embedded system, Electrical engineering and Voltage. The conference focuses on Electronic engineering but the discussions also offer insight into other areas such as Power (physics) and Reliability (semiconductor). International Conference on VLSI Design features CMOS research that overlaps with concepts in Energy harvesting.

It explores topics in Embedded system which can be helpful for research in disciplines like Distributed computing and Multi-core processor. The study on Electrical engineering presented in the event intersects with the topics under Capacitance. It addresses concerns in Voltage which are intertwined with other disciplines, such as Efficient energy use and Robustness (computer science).

The most cited articles from the last conference are:

  • Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage (32 citations)
  • BRAIN: BehavioR Based Adaptive Intrusion Detection in Networks: Using Hardware Performance Counters to Detect DDoS Attacks (31 citations)
  • Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in IoT Edge Devices (20 citations)

Papers citation over time

A key indicator for each conference is its effectiveness in reaching other researchers with the papers published at that venue.

The chart below presents the interquartile range (first quartile 25%, median 50% and third quartile 75%) of the number of citations of articles over time.


The top authors publishing at International Conference on VLSI Design (based on the number of publications) are:

  • Prabhat Mishra (10 papers) published 1 paper at the last edition, 1 less than at the previous edition,
  • S. K. Nandy (10 papers) published 5 papers at the last edition, 3 more than at the previous edition,
  • Ranjani Narayan (8 papers) published 4 papers at the last edition, 1 more than at the previous edition,
  • Kewal K. Saluja (8 papers) published 2 papers at the last edition the same number as at the previous edition,
  • Amit Patra (7 papers) absent at the last edition.

The overall trend for top authors publishing at this conference is outlined below. The chart shows the number of publications at each edition of the conference for top authors.


Only papers with recognized affiliations are considered

The top affiliations publishing at International Conference on VLSI Design (based on the number of publications) are:

  • Indian Institute of Technology Kharagpur (33 papers) published 9 papers at the last edition the same number as at the previous edition,
  • Indian Institute of Science (23 papers) published 8 papers at the last edition, 2 more than at the previous edition,
  • Indian Institute of Technology Guwahati (17 papers) published 12 papers at the last edition, 9 more than at the previous edition,
  • Indian Institute of Technology Bombay (14 papers) published 4 papers at the last edition the same number as at the previous edition,
  • IBM (14 papers) published 2 papers at the last edition, 1 less than at the previous edition.

The overall trend for top affiliations publishing at this conference is outlined below. The chart shows the number of publications at each edition of the conference for top affiliations.


Publication chance based on affiliation

The publication chance index shows the ratio of articles published by the best research institutions at the conference edition to all articles published within that conference. The best research institutions were selected based on the largest number of articles published during all editions of the conference.

The chart below presents the percentage ratio of articles from top institutions (based on their ranking of total papers).Top affiliations were grouped by their rank into the following tiers: top 1-10, top 11-20, top 21-50, and top 51+. Only articles with a recognized affiliation are considered.


During the most recent 2016 edition, 9.70% of publications had an unrecognized affiliation. Out of the publications with recognized affiliations, 37.19% were posted by at least one author from the top 10 institutions publishing at the conference. Another 18.18% included authors affiliated with research institutions from the top 11-20 affiliations. Institutions from the 21-50 range included 23.97% of all publications and 20.66% were from other institutions.

Returning Authors Index

A very common phenomenon observed among researchers publishing scientific articles is the intentional selection of conferences they have already attended in the past. In particular, it is worth analyzing the case when the authors participate in the same conference from year to year.

The Returning Authors Index presented below illustrates the ratio of authors who participated in both a given as well as the previous edition of the conference in relation to all participants in a given year.


Returning Institution Index

The graph below shows the Returning Institution Index, illustrating the ratio of institutions that participated in both a given and the previous edition of the conference in relation to all affiliations present in a given year.


The experience to innovation index

Our experience to innovation index was created to show a cross-section of the experience level of authors publishing at a conference. The index includes the authors publishing at the last edition of a conference, grouped by total number of publications throughout their academic career (P) and the total number of citations of these publications ever received (C).

The group intervals were selected empirically to best show the diversity of the authors' experiences, their labels were selected as a convenience, not as judgment. The authors were divided into the following groups:

  • Novice - P < 5 or C < 25 (the number of publications less than 5 or the number of citations less than 25),
  • Competent - P < 10 or C < 100 (the number of publications less than 10 or the number of citations less than 100),
  • Experienced - P < 25 or C < 625 (the number of publications less than 25 or the number of citations less than 625),
  • Master - P < 50 or C < 2500 (the number of publications less than 50 or the number of citations less than 2500),
  • Star - P ≥ 50 and C ≥ 2500 (both the number of publications greater than 50 and the number of citations greater than 2500).


The chart below illustrates experience levels of first authors in cases of publications with multiple authors.


Other Conferences in India

19th Asia Pacific Conference on Circuits and Systems

Nov 20, 2023 - Nov 23, 2023

Hyderabad, India

Deadline: Sunday 04 Jun 2023

7th IEEE International Test Conference

Jul 23, 2023 - Jul 25, 2023

Bengaluru, India

Deadline: Monday 06 Feb 2023

Previous Editions

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